College of Electrical Engineering and Computer Science

Student theses

A Low-Cost VLSI Architecture of Bilateral Filter for Image Denoising

Author: 悅翎, 鄧., 2016 Feb 4

Supervisor: Chen, P. (Supervisor)

Student thesis: Master's Thesis

A Low Energy Consumption 10-Bit 100kS/s SAR ADC with Time-based Adaptive Window

Author: 致遠, 孔., 2018 Aug 31

Supervisor: Chang, S. (Supervisor)

Student thesis: Master's Thesis

A Low-Latency Warrants Trading Scheme of Risk Management Using NetFPGA SUME

Author: 偉立, 王., 2018 Aug 21

Supervisor: Chang, Y. (Supervisor)

Student thesis: Master's Thesis

A Low Power 10-Bit SAR ADC with DT-MOS at Ultra-Low Supply Voltage

Author: 豪廷, 簡., 2018 Sep 7

Supervisor: Chang, S. (Supervisor)

Student thesis: Master's Thesis

A Low Power and High Resolution Pipelined SAR ADC with Loading-Free Architecture

Author: 佳璋, 吳., 2014 May 19

Supervisor: Chang, S. (Supervisor)

Student thesis: Master's Thesis

A Low Power Duobinary Voltage-Mode Transmitter

Author: 銘宏, 簡., 2017 Oct 31

Supervisor: Chang, S. (Supervisor)

Student thesis: Master's Thesis

A Low Power Multi-Channel FSK Transmitter with Injection Locking Technique

Author: 文浩, 何., 2014 Aug 13

Supervisor: Cheng, K. (Supervisor)

Student thesis: Master's Thesis

A Low-Power Quadrature Phase Shift Keying Transmitter with Injection Locking Technique

Author: 上德, 楊., 2017 Jan 19

Supervisor: Cheng, K. (Supervisor)

Student thesis: Master's Thesis

A Memory Efficient DFA using Compression and Pattern Segmentation

Author: 袁碩, 李., 2014 Sep 3

Supervisor: Chang, Y. (Supervisor)

Student thesis: Master's Thesis

A Memory-Efficient NoC System for Manycore Platform

Author: 健瑄, 嚴., 2014 Aug 22

Supervisor: Chen, C. (Supervisor)

Student thesis: Master's Thesis

A Memory Efficient Regular Expression Matching Scheme in ClamAV Anti-Virus System

Author: 奕賢, 吳., 2018 Sep 5

Supervisor: Chang, Y. (Supervisor)

Student thesis: Master's Thesis

A Message-Handover Protocol at Intersection in Vehicular Ad Hoc Networks

Author: 承浩, 吳., 2014 Aug 1

Supervisor: Sou, S. (Supervisor)

Student thesis: Master's Thesis

A Metaheuristic Multi-Constraint Routing Mechanism for Traffic Scheduling in Software-Defined Networking

Author: 裕穎, 鄭., 2018 Aug 31

Supervisor: Lin, H. (Supervisor)

Student thesis: Master's Thesis

A Method for Improving Read Performance on Multilevel-Cell NAND Flash Storage

Author: 偉誠, 林., 2016 Apr 21

Supervisor: Chang, D. (Supervisor)

Student thesis: Master's Thesis

A Method to Improve Human Error Caused by Network Delay

Author: 健富, 廖., 2016 Aug 22

Supervisor: Tsai, P. (Supervisor)

Student thesis: Master's Thesis

A Modified Functional Observer-based EID Estimator for Unknown Analog Singular Systems

Author: 彥芳, 陳., 2018 Jul 30

Supervisor: Tsai, J. S. (Supervisor)

Student thesis: Master's Thesis

A Modified Functional Observer-based EID Estimator for Unknown Sampled-data Singular Systems

Author: 嘉元, 張., 2018 Jul 30

Supervisor: Tsai, J. S. (Supervisor)

Student thesis: Master's Thesis

A Modified Synthetic Aperture Focusing Technique Utilizing Beam Characteristics of Transducer for Ultrasound Image Improvement

Author: 嘉哲, 何., 2014 Sep 2

Supervisor: Wang, S. (Supervisor)

Student thesis: Master's Thesis

A Modified Time-Frequency Transform and Its Application to Power Quality Signal Supervision

Author: 江永, 承., 2016 Mar 25

Supervisor: Huang, S. (Supervisor)

Student thesis: Doctoral Thesis

A Multi-Core Multi-Tasking Arduino Compatible FPGA System

Author: 增穎, 韓., 2017 Aug 23

Supervisor: Su, W. (Supervisor)

Student thesis: Master's Thesis

An 11-Bit 20-MS/s Wide Input Range Successive-Approximation Analog-to-Digital Converter

Author: 文佳, 羅., 2019

Supervisor: Chang, S. (Supervisor)

Student thesis: Master's Thesis

An 8-bit 2GS/s Flash ADC with Step-Shifted Background Offset Calibration

Author: 君豪, 張., 2014 Aug 1

Supervisor: Kuo, T. (Supervisor)

Student thesis: Master's Thesis

An 8-bit 400-MS/s Calibration-Free SAR ADC with a Pre-amplifier-only Comparator

Author: 智輝, 侯., 2016 Nov 15

Supervisor: Chang, S. (Supervisor)

Student thesis: Master's Thesis

An 8 Gb/s Half-rate Digital-based Clock and Data Recovery Circuit With Compact Control Loop

Author: 宇栢, 鄭., 2015 Aug 21

Supervisor: Chang, S. (Supervisor)

Student thesis: Master's Thesis

An adaptive cost aggregation method based on bilateral filter and Canny edge detector with segmented area for stereo matching

Author: 子雄, 蔡., 2014 Aug 18

Supervisor: Chung, P. (Supervisor)

Student thesis: Master's Thesis