Cheng-Wen Wu

Professor

  • 4818 Citations
  • 36 h-Index
1985 …2019
If you made any changes in Pure these will be visible here soon.

Research Output 1985 2019

Filter
Conference contribution
2019

A Self-Organizing Map-Based Adaptive Traffic Light Control System with Reinforcement Learning

Kao, Y. C. & Wu, C. W., 2019 Feb 19, Conference Record of the 52nd Asilomar Conference on Signals, Systems and Computers, ACSSC 2018. Matthews, M. B. (ed.). IEEE Computer Society, p. 2060-2064 5 p. 8645125. (Conference Record - Asilomar Conference on Signals, Systems and Computers; vol. 2018-October).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Self organizing maps
Reinforcement learning
Telecommunication traffic
Control systems
Learning systems

Solutions to Multiple Probing Challenges for Test Access to Multi-Die Stacked Integrated Circuits

Marinissen, E. J., Fodor, F., Podpod, A., Stucchi, M., Jian, Y. R. & Wu, C. W., 2019 Jan 23, International Test Conference 2018, ITC 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 8624731. (Proceedings - International Test Conference; vol. 2018-October).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Integrated Circuits
Integrated circuits
Die
Probe
Wafer
2018

A Built-in Self-Test Scheme for Detecting Defects in FinFET-Based SRAM Circuit

Chen, M. C., Wu, T. H. & Wu, C. W., 2018 Dec 6, Proceedings - 2018 IEEE 27th Asian Test Symposium, ATS 2018. IEEE Computer Society, p. 19-24 6 p. 8567404. (Proceedings of the Asian Test Symposium; vol. 2018-October).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Built-in self test
Static random access storage
Defects
Networks (circuits)
Transistors

A Deep Learning-Based Screening Method for Improving the Quality and Reliability of Integrated Passive Devices

Pan, Y-C., Jian, Y-R., Liu, H-H. & Wu, C-W., 2018 Jul, VLSI Test Technology Workshop (VTTW). Nantou

Research output: Chapter in Book/Report/Conference proceedingConference contribution

An enhanced boundary scan architecture for inter-die interconnect leakage measurement in 2.5D and 3D packages

Law, P. M. P., Wu, C. W., Lin, L. Y. & Hong, H. C., 2018 Jan 24, Proceedings - 2017 IEEE 26th Asian Test Symposium, ATS 2017. Taipei: IEEE Computer Society, p. 1-6 6 p. (Proceedings of the Asian Test Symposium).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Leakage currents
Packaging
Defects
Fans
Built-in self test

Automated Probe-Mark Analysis

Wu, C-W., Jian, Y-R., Fodor, F. & Marinissen, E. J., 2018 Jun, Semiconductor Wafer Test Workshop (SWTW).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Covering hard-To-detect defects by thermal quorum sensing

Chuang, P. Y., Wu, C. W. & Chen, H. H., 2018 Jun 29, Proceedings - 2018 23rd IEEE European Test Symposium, ETS 2018. Bremen: Institute of Electrical and Electronics Engineers Inc., p. 1-2 2 p. (Proceedings of the European Test Workshop; vol. 2018-May).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Defects
Networks (circuits)
Testing
Cells
Hot Temperature

RRAM-based neuromorphic hardware reliability improvement by self-healing and error correction

Hu, J. Y., Hou, K. W., Lo, C. Y., Chou, Y. F. & Wu, C. W., 2018 Sep 11, Proceedings - 2nd IEEE International Test Conference in Asia, ITC-Asia 2018. Institute of Electrical and Electronics Engineers Inc., p. 19-24 6 p. 8462942. (Proceedings - 2nd IEEE International Test Conference in Asia, ITC-Asia 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Error correction
Memristors
Neural networks
Hardware
Degradation

Symbiotic Controller Design Using a Memory-Based FSM Model

Kuo, S. F. & Wu, C. W., 2018 Aug 10, Proceedings - 2018 IEEE 27th International Symposium on Industrial Electronics, ISIE 2018. Institute of Electrical and Electronics Engineers Inc., p. 874-879 6 p. 8433783. (IEEE International Symposium on Industrial Electronics; vol. 2018-June).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Data storage equipment
Controllers
Energy utilization
Costs
Telecommunication traffic
2017

Cell-Aware Test Generation Time Reduction by Using Switch-Level ATPG

Wu, C-W., Chuang, P-Y. & Chen, H. H., 2017 Sep, IEEE Int. Test Conf. in Asia (ITC-A). Taipei

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Fault Models and Test Algorithms for Multi-Level Cell (MLC) Crossbar RRAM

Wu, C-W. & Hou, K-W., 2017 Jul, VLSI Test Technology Workshop (VTTW). Nantou

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Highly Reliable and Low-Cost Symbiotic IOT Devices and Systems

Wu, C-W., Lin, B-Y., Hung, H-W., Tseng, S-M. & Chen, C., 2017 Oct, IEEE Int. Test Conf. (ITC). Fort Worth, Texas

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Symbiotic system models for efficient IGT system design and test

Wu, C. W., Lin, B. Y., Hung, H. W., Tseng, S. M. & Chen, C., 2017 Nov 3, ITC-Asia 2017 - International Test Conference in Asia. Institute of Electrical and Electronics Engineers Inc., p. 71-76 6 p. 8097114. (ITC-Asia 2017 - International Test Conference in Asia).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Insulated gate bipolar transistors (IGBT)
Systems analysis
Energy utilization
Costs
Repair

Symbiotic System Models for Efficient IOT System Design and Test

Wu, C-W., Chen, C., Lin, B-Y., Hung, H-W. & Tseng, S-M., 2017 Sep, IEEE Int. Test Conf. in Asia (ITC-A). Taipei

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2016
2 Citations (Scopus)

A fast sweep-line-based failure pattern extractor for memory diagnosis

Wei, S. Y., Lin, B. Y. & Wu, C. W., 2016 Jul 22, Proceedings - 2016 21st IEEE European Test Symposium, ETS 2016. Institute of Electrical and Electronics Engineers Inc., 7519314. (Proceedings of the European Test Workshop; vol. 2016-July).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Data storage equipment
Product development
Experiments
4 Citations (Scopus)

Efficient Cell-Aware Fault Modeling by Switch-Level Test Generation

Chen, H. H., Chen, S. Y. H., Chuang, P. Y. & Wu, C. W., 2016 Dec 22, Proceedings - 2016 IEEE 25th Asian Test Symposium, ATS 2016. IEEE Computer Society, p. 197-202 6 p. 7796112. (Proceedings of the Asian Test Symposium).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Transistors
Switches
Defects
Circuit simulation
Electric network analysis
1 Citation (Scopus)

Efficient probing schemes for fine-pitch pads of InFO wafer-level chip-scale package

Huang, Y. C., Lin, B. Y., Wu, C. W., Lee, M., Chen, H., Lin, H. C., Peng, C. N. & Wang, M. J., 2016 Jun 5, Proceedings of the 53rd Annual Design Automation Conference, DAC 2016. Institute of Electrical and Electronics Engineers Inc., a58. (Proceedings - Design Automation Conference; vol. 05-09-June-2016).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Chip scale packages
Wafer
Fans
Packaging
Chip
2 Citations (Scopus)

Layout-Oriented Defect Set Reduction for Fast Circuit Simulation in Cell-Aware Test

Liu, H. W., Lin, B. Y. & Wu, C. W., 2016 Dec 22, Proceedings - 2016 IEEE 25th Asian Test Symposium, ATS 2016. IEEE Computer Society, p. 156-160 5 p. 7796105. (Proceedings of the Asian Test Symposium).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Circuit simulation
Defects
Transistors
Resistors
Capacitors

Symbiotic-System Approach for IOT Devices

Wu, C-W., 2016 Nov, 25th IEEE Asian Test Symp. (ATS), Hiroshima. Hiroshima

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2015
2 Citations (Scopus)

A Computer Designed Half Gb 16-Channel 819Gb/s High-Bandwidth and 10ns Low-Latency DRAM for 3D Stacked Memory Devices Using TSVs

Wu, C-W., Luo, P-W., Chen, C-K., Sung, Y-H., Wu, W., Shih, H-C., Lee, C-H., Lee, K-H., Li, M-W., Lung, M-C., Lu, C-N., Chou, Y-F., Shih, P-L., Ke, C-H., Shiah, C., Stolt, P., Tomishima, S., Kwai, D-M., Rong, B-D., Lu, N. & 1 others, Lu, S-L., 2015 Jun, IEEE Symp. VLSI Circuits (VLSI).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Redundancy architectures for channel-based 3D DRAM yield improvement

Lin, B. Y., Chiang, W. T., Wu, C. W., Lee, M., Lin, H. C., Peng, C. N. & Wang, M. J., 2015 Feb 6, Proceedings - 2014 IEEE International Test Conference, ITC 2014. Seattle, Washington: Institute of Electrical and Electronics Engineers Inc., 7035331. (Proceedings - International Test Conference; vol. 2015-February).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Random Access
Redundancy
Die
Data storage equipment
Logic

System-level test coverage prediction by structural stress test data mining

Lin, B. Y., Wu, C. W. & Chen, H. H., 2015 May 28, 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015. Institute of Electrical and Electronics Engineers Inc., 7114508. (2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Program processors
Data mining
Learning systems
Silicon
Electric potential
2014
1 Citation (Scopus)

BIST-assisted tuning scheme for minimizing io-channel power of TSV-based 3D DRAMs

Yu, Y. C., Yang, C. C., Li, J. F., Lo, C. Y., Chen, C. H., Lai, J. S., Kwai, D. M., Chou, Y. F. & Wu, C. W., 2014 Dec 7, Proceedings - 23rd Asian Test Symposium, ATS 2014. Hsinchu: IEEE Computer Society, p. 1-6 6 p. 06979068. (Proceedings of the Asian Test Symposium).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Built-in self test
Dynamic random access storage
Tuning
Silicon
Data storage equipment

DRAM system simulation speed-Up by effective-cycle selection

Chiang, H. C., Wang, M. Y. & Wu, C. W., 2014 Jan 1, Proceedings - 2014 International Symposium on Computer, Consumer and Control, IS3C 2014. IEEE Computer Society, p. 1053-1056 4 p. 6846067. (Proceedings - 2014 International Symposium on Computer, Consumer and Control, IS3C 2014).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Dynamic random access storage
Redundancy
Data storage equipment
Simulators
Systems analysis
2013
32 Citations (Scopus)

3D-IC interconnect test, diagnosis, and repair

Chi, C. C., Wu, C. W., Wang, M. J. & Lin, H. C., 2013 Aug 14, Proceedings - 2013 IEEE 31st VLSI Test Symposium, VTS 2013. 6548905. (Proceedings of the IEEE VLSI Test Symposium).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Repair
Defects
Cost benefit analysis
Profitability
Silicon
19 Citations (Scopus)

A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS

Lin, T. J., Chien, C. A., Chang, P. Y., Chen, C. W., Wang, P. H., Shyu, T. Y., Chou, C. Y., Luo, S. C., Guo, J. I., Chen, T. F., Chuang, G. C. H., Chu, Y. H., Cheng, L. C., Su, H. M., Jou, C., Ieong, M., Wu, C. W. & Wang, J. S., 2013 Apr 29, 2013 IEEE International Solid-State Circuits Conference, ISSCC 2013 - Digest of Technical Papers. p. 158-159 2 p. 6487680. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; vol. 56).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Video recording
Static random access storage
ROM
Pixels
Macros
5 Citations (Scopus)

A hybrid ECC and redundancy technique for reducing refresh power of DRAMs

Yu, Y. C., Hou, C. S., Chang, L. J., Li, J. F., Lo, C. Y., Kwai, D. M., Chou, Y. F. & Wu, C. W., 2013 Aug 14, Proceedings - 2013 IEEE 31st VLSI Test Symposium, VTS 2013. 6548927. (Proceedings of the IEEE VLSI Test Symposium).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Dynamic random access storage
Redundancy
Data storage equipment
Networks (circuits)
Error correction
1 Citation (Scopus)

Analytical modeling and numerical simulations of temperature field in TSV-based 3D ICs

Shiyanovskii, Y., Papachristou, C. & Wu, C. W., 2013 Jul 5, Proceedings of the 14th International Symposium on Quality Electronic Design, ISQED 2013. p. 24-29 6 p. 6523585. (Proceedings - International Symposium on Quality Electronic Design, ISQED).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Temperature distribution
Silicon
Computer simulation
Electric heating
Heat transfer
2 Citations (Scopus)

An enhanced double-TSV Scheme for defect tolerance in 3D-IC

Shih, H. C. & Wu, C. W., 2013 Oct 21, Proceedings - Design, Automation and Test in Europe, DATE 2013. p. 1486-1489 4 p. 6513748. (Proceedings -Design, Automation and Test in Europe, DATE).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Silicon
Defects
Electric fuses
Repair
Electric power utilization
10 Citations (Scopus)

An FPGA-based test platform for analyzing data retention time distribution of DRAMs

Hou, C. S., Li, J. F., Lo, C. Y., Kwai, D. M., Chou, Y. F. & Wu, C. W., 2013 Aug 15, 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013. 6533853. (2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Dynamic random access storage
Field programmable gate arrays (FPGA)
Data storage equipment
Electric potential
Temperature

Exploration Methodology for 3D Memory Redun- dancy Architectures under Redundancy Constraints

Wu, C-W., Lin, B-Y. & Lee, M., 2013 Nov, 22nd IEEE Asian Test Symp. (ATS). Yilan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Failure-Pattern-Based Test Data Compression for Memories

Wu, C-W., Lin, B-Y. & Lee, M., 2013 Jul, VLSI Test Technology Workshop (VTTW). New Taipei City

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Processor and DRAM integration by TSV-based 3-D stacking for power-aware SOCs

Chen, S. S., Hsu, C. K., Shih, H. C., Yeh, J. C. & Wu, C. W., 2013 May 20, 2013 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013. p. 429-434 6 p. 6509634. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Dynamic random access storage
Mobile devices
Energy efficiency
Experiments
2012
9 Citations (Scopus)

3D-IC BISR for stacked memories using cross-die spares

Chi, C. C., Chou, Y. F., Kwai, D. M., Hsiao, Y. Y., Wu, C. W., Hsing, Y. T., Denq, L. M. & Lin, T. H., 2012 Jul 25, 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers. 6212621. (2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Data storage equipment
Repair
Silicon
Networks (circuits)
4 Citations (Scopus)

A built-in self-test scheme for 3D RAMs

Yu, Y. C., Chou, C. W., Li, J. F., Lo, C. Y., Kwai, D. M., Chou, Y. F. & Wu, C. W., 2012 Dec 1, ITC 2012 - International Test Conference 2012, Proceedings. 6401579. (Proceedings - International Test Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Built-in Self-test
Built-in self test
Random access storage
Die
Networks (circuits)
9 Citations (Scopus)

A memory failure pattern analyzer for memory diagnosis and repair

Lin, B. Y., Lee, M. & Wu, C. W., 2012 Aug 20, Proceedings - 2012 30th IEEE VLSI Test Symposium, VTS 2012. p. 234-239 6 p. 6231059. (Proceedings of the IEEE VLSI Test Symposium).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Repair
Data storage equipment
Defects
Poisson distribution
Failure analysis
16 Citations (Scopus)

A memory yield improvement scheme combining built-in self-repair and error correction codes

Wu, T. H., Chen, P. Y., Lee, M., Lin, B. Y., Wu, C. W., Tien, C. H., Lin, H. C., Chen, H., Peng, C. N. & Wang, M. J., 2012 Dec 1, ITC 2012 - International Test Conference 2012, Proceedings. 6401576. (Proceedings - International Test Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Error correction
Error Correction
Repair
Data storage equipment
Redundancy
9 Citations (Scopus)

Cost modeling and analysis for interposer-based three-dimensional IC

Chou, Y. W., Chen, P. Y., Lee, M. & Wu, C. W., 2012 Aug 20, Proceedings - 2012 30th IEEE VLSI Test Symposium, VTS 2012. p. 108-113 6 p. 6231088. (Proceedings of the IEEE VLSI Test Symposium).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Costs
Three dimensional integrated circuits
Integrated circuits
Data storage equipment
Silicon
13 Citations (Scopus)

On test and repair of 3D random access memory

Wu, C. W., Lu, S. K. & Li, J. F., 2012 Apr 26, ASP-DAC 2012 - 17th Asia and South Pacific Design Automation Conference. p. 744-749 6 p. 6165054. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Repair
Random access storage
Data storage equipment
Redundancy
Heuristic algorithms

Welcome message

Wu, C. W. & Huang, J. L., 2012 Nov 6, Proceedings of the 2012 IEEE 18th International Mixed-Signal, Sensors, and Systems Test Workshop, IMS3TW 2012. p. viii 6298735. (Proceedings of the 2012 IEEE 18th International Mixed-Signal, Sensors, and Systems Test Workshop, IMS3TW 2012).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2011
63 Citations (Scopus)

A built-in self-test scheme for the post-bond test of TSVs in 3D ICs

Huang, Y. J., Li, J. F., Chen, J. J., Kwai, D. M., Chou, Y. F. & Wu, C. W., 2011 Jul 1, Proceedings - 2011 29th IEEE VLSI Test Symposium, VTS 2011. p. 20-25 6 p. 5783749. (Proceedings of the IEEE VLSI Test Symposium).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Built-in self test
Networks (circuits)
Silicon
Costs
Integrated circuits
2 Citations (Scopus)

A low-cost wireless interface with no external antenna and crystal oscillator for Cm-range contactless testing

Li, C. F., Lee, C. Y., Wang, C. H., Chang, S. L., Denq, L. M., Chi, C. C., Hsu, H. J., Chu, M. Y., Liou, J. J., Huang, S. Y., Huang, P. C., Ma, H. P., Bor, J. C., Wu, C. W., Tien, C. C., Wang, C. H., Kuo, Y. S., Huang, C. T. & Chang, T. Y., 2011 Sep 16, 2011 48th ACM/EDAC/IEEE Design Automation Conference, DAC 2011. p. 771-776 6 p. 5981870. (Proceedings - Design Automation Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Crystal oscillators
Antenna
Crystal
Antennas
Testing
11 Citations (Scopus)

A self-testing and calibration method for embedded successive approximation register ADC

Huang, X. L., Kang, P. Y., Chang, H. M., Huang, J. L., Chou, Y. F., Lee, Y. P., Kwai, D. M. & Wu, C. W., 2011 Mar 28, 2011 16th Asia and South Pacific Design Automation Conference, ASP-DAC 2011. p. 713-718 6 p. 5722279. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Digital to analog conversion
Calibration
Testing
Codes (standards)
Capacitors

Built-in self-forming, built-in self-test, and built-in self-repair for RRAM yield improvement

Wu, C-W., Chen, C-Y., Shih, H-C., Lee, M., Lin, C-H. & Sheu, S-S., 2011 Jul, VLSI Test Tech. Workshop (VTTW). Nantou

Research output: Chapter in Book/Report/Conference proceedingConference contribution

28 Citations (Scopus)

DfT architecture for 3D-SICs with multiple towers

Chi, C. C., Marinissen, E. J., Goel, S. K. & Wu, C. W., 2011 Aug 29, Proceedings - 16th IEEE European Test Symposium, ETS 2011. p. 51-56 6 p. 5957922. (Proceedings - 16th IEEE European Test Symposium, ETS 2011).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Design for testability
Towers
Product design
Costs
Silicon
13 Citations (Scopus)

Multi-visit TAMs to reduce the post-bond test length of 2.5D-SICs with a passive silicon interposer base

Chi, C. C., Marinissen, E. J., Goel, S. K. & Wu, C. W., 2011 Dec 1, Proceedings of the 20th Asian Test Symposium, ATS 2011. p. 451-456 6 p. 6114771. (Proceedings of the Asian Test Symposium).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Silicon
Towers
Hardware
Testing
Costs

Special session: Hot topic design and test of 3D and emerging memories

Wu, C. W., 2011 Jul 1, Proceedings - 2011 29th IEEE VLSI Test Symposium, VTS 2011. 1 p. 5783744. (Proceedings of the IEEE VLSI Test Symposium).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Data storage equipment
Dynamic random access storage
9 Citations (Scopus)

Training-based forming process for RRAM yield improvement

Shih, H. C., Chen, C. Y., Wu, C. W., Lin, C. H. & Sheu, S. S., 2011 Jul 1, Proceedings - 2011 29th IEEE VLSI Test Symposium, VTS 2011. p. 146-151 6 p. 5783775. (Proceedings of the IEEE VLSI Test Symposium).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Data storage equipment
Networks (circuits)
RRAM
Testing
2010
3 Citations (Scopus)

AF-test: Adaptive-frequency scan test methodology for small-delay defects

Li, T. Y., Huang, S. Y., Hsu, H. J., Tzeng, C. W., Huang, C. T., Liou, J. J., Ma, H. P., Huang, P. C., Bor, J. C., Wu, C. W., Tien, C. C. & Wang, M., 2010 Dec 1, Proceedings - 2010 25th International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010. p. 340-348 9 p. 5634926. (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Clocks
Defects
Phase locked loops
Networks (circuits)
Testing
6 Citations (Scopus)

A low-cost and scalable test architecture for multi-core chips

Chi, C. C., Wu, C. W. & Li, J. F., 2010 Nov 3, 2010 15th IEEE European Test Symposium, ETS'10. p. 30-35 6 p. 5512784. (2010 15th IEEE European Test Symposium, ETS'10).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Cryptography
Costs
Scalability
Pipelines