If you made any changes in Pure these will be visible here soon.

Personal profile

Education

  • 2011 PhD, University of California, Berkeley, USA

Research Interests

  • Compact Device Modeling for NCFET
  • Compact Device Modeling for the FinFET and UTBSOI MOSFETs
  • Hardware Realization of AI Deep Learning
  • Nanofabrication of M-I-M Devices for Resistive Memory Applications
  • Numerical Simulation of Semiconductor Processes and Devices FinFET (TCAD)

Experience

  • 2008/7~2008/9 Engineering Intern, IBM Semiconductor Research and Development Center, New York, USA
  • 2010/1~2010/5 Research Intern, IBM Thomas J. Watson Research Lab, New York, USA
  • 2011/8~2015/8 Research Scientist, IBM Thomas J. Watson Research Lab, New York, USA
  • 2015/8~present Assistant Professor, Department of Electrical Engineering, National Cheng Kung University

Fingerprint Dive into the research topics where Darsen Lu is active. These topic labels come from the works of this person. Together they form a unique fingerprint.

  • 9 Similar Profiles

Network Recent external collaboration on country level. Dive into details by clicking on the dots.

Projects

Research Output

Fabrication of omega-gated negative capacitance finfets and SRAM

Sung, P. J., Su, C. J., Lu, D. D., Luo, S. X., Kao, K. H., Ciou, J. Y., Jao, C. Y., Hsu, H. S., Wang, C. J., Hong, T. C., Liao, T. H., Fang, C. C., Wang, Y. S., Huang, H. F., Li, J. H., Huang, Y. C., Hsueh, F. K., Wu, C. T., Ma, W. C. Y., Huang, K. P. & 6 others, Lee, Y. J., Chao, T. S., Li, J. Y., Wu, W. F., Yeh, W. K. & Wang, Y. H., 2019 Apr, 2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019. Institute of Electrical and Electronics Engineers Inc., 8804663. (2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • 1 Citation (Scopus)

    Impact of Semiconductor Permittivity Reduction on Electrical Characteristics of Nanoscale MOSFETs

    Chen, S. H., Lian, S. W., Wu, T. R., Chang, T. R., Liou, J. M., Lu, D. D., Kao, K. H., Chen, N. Y., Lee, W. J. & Tsai, J. H., 2019 Jun, In : IEEE Transactions on Electron Devices. 66, 6, p. 2509-2512 4 p., 8704283.

    Research output: Contribution to journalArticle

  • An FET with a Source Tunneling Barrier Showing Suppressed Short-Channel Effects for Low-Power Applications

    Hsieh, Y. F., Chen, S. H., Chen, N. Y., Lee, W. J., Tsai, J. H., Chen, C. N., Chiang, M-H., Lu, D. & Kao, K-H., 2018 Mar 1, In : IEEE Transactions on Electron Devices. 65, 3, p. 855-859 5 p.

    Research output: Contribution to journalArticle

  • 1 Citation (Scopus)

    Emerging NVM circuit techniques and implementations for energy-efficient systems

    Khwa, W. S., Lu, D., Dou, C. M. & Chang, M. F., 2018 Jan 1, Beyond-CMOS Technologies for Next Generation Computer Design. Springer International Publishing, p. 85-132 48 p.

    Research output: Chapter in Book/Report/Conference proceedingChapter

  • 1 Citation (Scopus)

    FinFET with encased air-gap spacers for high-performance and low-energy circuits

    Sachid, A. B., Huang, Y. M., Chen, Y. J., Chen, C. C., Lu, D. D., Chen, M. C. & Hu, C., 2017 Jan, In : IEEE Electron Device Letters. 38, 1, p. 16-19 4 p., 7744575.

    Research output: Contribution to journalArticle

  • 17 Citations (Scopus)

    Thesis

    金屬-絕緣層-金屬 二極體之特性研究

    Author: 逸軒, 陳., 2016 Aug 12

    Supervisor: Lu, D. (Supervisor)

    Student thesis: Master's Thesis