Projects per year
Personal profile
Education
- 2011 PhD, University of California, Berkeley, USA
Research Interests
- Compact Device Modeling for NCFET
- Compact Device Modeling for the FinFET and UTBSOI MOSFETs
- Hardware Realization of AI Deep Learning
- Nanofabrication of M-I-M Devices for Resistive Memory Applications
- Numerical Simulation of Semiconductor Processes and Devices FinFET (TCAD)
Experience
- 2008/7~2008/9 Engineering Intern, IBM Semiconductor Research and Development Center, New York, USA
- 2010/1~2010/5 Research Intern, IBM Thomas J. Watson Research Lab, New York, USA
- 2011/8~2015/8 Research Scientist, IBM Thomas J. Watson Research Lab, New York, USA
- 2015/8~present Assistant Professor, Department of Electrical Engineering, National Cheng Kung University
Expertise related to UN Sustainable Development Goals
In 2015, UN member states agreed to 17 global Sustainable Development Goals (SDGs) to end poverty, protect the planet and ensure prosperity for all. This person’s work contributes towards the following SDG(s):
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SDG 7 Affordable and Clean Energy -
SDG 9 Industry, Innovation, and Infrastructure
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Collaborations and top research areas from the last five years
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Projects
- 9 Finished
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以前瞻非揮發性記憶體為中心適用於大規模平行化之容錯且可重組的異質運算平台-非揮發記憶元件之計算記憶體電路模型
Lu, D. (PI)
21-08-01 → 22-07-31
Project: Research project
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A Compact Gray-Code Quantum Read-only Memory for the NISQ Era
Lu, H. Y., Kao, Y. T., Chang, Y. J., Wang, C.-H. & Lu, D., 2026, Proceedings of the 27th International Symposium on Quality Electronic Design, ISQED 2026. IEEE Computer Society, (Proceedings - International Symposium on Quality Electronic Design, ISQED).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
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Direct Extraction of Fowler–Nordheim Tunneling Parameters of Asymmetric Metal-Insulator-Metal Diodes Based on Current-Voltage Measurement
Lin, W. & Lu, D. D., 2026, In: IEEE Journal of the Electron Devices Society. 14, p. 18-23 6 p.Research output: Contribution to journal › Article › peer-review
Open Access -
Hardware-Efficient Quantum Grid Sampling for Low-Latency Amplitude Estimation
Kao, Y. T., Lu, H. Y., Chang, Y. J., Young, J. G., Wang, C. H. & Lu, D. D., 2026, In: Proceedings of the IEEE Dallas Circuits and Systems Conference, DCAS. 2026Research output: Contribution to journal › Conference article › peer-review
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Sub-2 nm Equivalent-Oxide-Thickness Ferroelectric Transistors for Cryogenic Memory and Computing
Das, A., Senapati, A., Kumar, G., Lou, Z. F., Müller, J., Maskeen, J. S., Chang, Y. T., Tewari, M., Agarwal, A., Paul, A., Raffel, Y., Maikap, S., Kao, K. H., Agarwal, T., Lashkare, S., Lu, D., Larrieu, G., Lee, M. H. & De, S., 2026 Apr 14, In: ACS nano. 20, 14, p. 10905-10918 14 p.Research output: Contribution to journal › Article › peer-review
Open Access1 Link opens in a new tab Citation (Scopus) -
Demonstration of Nanoscale Cryogenic Ferroelectric Independent-Double-Gate FinFET for High-Density Storage and Neuromorphic Computing
Lu, H. Y., Lee, H. M., Zhong, S. L., Liang, C. K., Hsu, S. T., Pai, Y. C., Tseng, W. C., Baig, M. A., Le, H. H., Chen, N. Y., Lee, W. J., Wang, C. H., Kao, K. H., Chiang, M.-H., Lee, Y. J., Wang, Y. H. & Lu, D. D., 2025, Proceedings - 51st IEEE European Solid-State Electronics Research Conference, ESSERC 2025. IEEE Computer Society, p. 265-268 4 p. (European Solid-State Circuits Conference).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution