Projects per year
Personal profile
Education
- 2011 PhD, University of California, Berkeley, USA
Research Interests
- Compact Device Modeling for NCFET
- Compact Device Modeling for the FinFET and UTBSOI MOSFETs
- Hardware Realization of AI Deep Learning
- Nanofabrication of M-I-M Devices for Resistive Memory Applications
- Numerical Simulation of Semiconductor Processes and Devices FinFET (TCAD)
Experience
- 2008/7~2008/9 Engineering Intern, IBM Semiconductor Research and Development Center, New York, USA
- 2010/1~2010/5 Research Intern, IBM Thomas J. Watson Research Lab, New York, USA
- 2011/8~2015/8 Research Scientist, IBM Thomas J. Watson Research Lab, New York, USA
- 2015/8~present Assistant Professor, Department of Electrical Engineering, National Cheng Kung University
Expertise related to UN Sustainable Development Goals
In 2015, UN member states agreed to 17 global Sustainable Development Goals (SDGs) to end poverty, protect the planet and ensure prosperity for all. This person’s work contributes towards the following SDG(s):
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Collaborations and top research areas from the last five years
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Projects
- 9 Finished
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以前瞻非揮發性記憶體為中心適用於大規模平行化之容錯且可重組的異質運算平台-非揮發記憶元件之計算記憶體電路模型
Lu, D. (PI)
21-08-01 → 22-07-31
Project: Research project
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A Hardware Friendly Variation-Tolerant Framework for RRAM-Based Neuromorphic Computing
Gu, F. Y., Yang, C. H., Lin, I. C., Chang, D. W., Lu, D. D. & Schlichtmann, U., 2024, In: IEEE Transactions on Circuits and Systems I: Regular Papers. 71, 12, p. 6419-6432 14 p.Research output: Contribution to journal › Article › peer-review
4 Citations (Scopus) -
CIMulator: Evaluating Neuromorphic Accelerators with HZO FefinFET-Based Synaptic Device
Le, H. H., Lu, H. Y., Baig, M. A., De, S., Lin, I. C. & Lu, D. D., 2024, Proceedings of 2024 7th International Conference on Green Technology and Sustainable Development, GTSD 2024. Institute of Electrical and Electronics Engineers Inc., p. 500-503 4 p. (Proceedings of 2024 7th International Conference on Green Technology and Sustainable Development, GTSD 2024).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
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Heterogeneous CFET: A Pathway to CMOS Performance Balance Engineering
Yu, X. R., Lu, W. H., Chang, S. W., Chang, W. H., Lu, D. D., Lee, Y. J., Maeda, T., Wu, W. F., Li, Y. M. & Wang, Y. H., 2024, 2024 IEEE Silicon Nanoelectronics Workshop, SNW 2024. Institute of Electrical and Electronics Engineers Inc., p. 5-6 2 p. (2024 IEEE Silicon Nanoelectronics Workshop, SNW 2024).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
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Numerical Simulations of Gate-Granularity- Induced Subthreshold Characteristics Deterioration of MOSFETs Magnified at Cryogenic Temperatures
Kao, K. H., Wang, Z. H., Pai, Y. C., Cheng, C. C., Lu, D. D., Lee, W. J. & Chen, N. Y., 2024, In: IEEE Access. 12, p. 169748-169754 7 p.Research output: Contribution to journal › Article › peer-review
Open Access1 Citation (Scopus) -
3-D Monolithic Stacking of Complementary-FET on CMOS for Next Generation Compute-In-Memory SRAM
Baig, M. A., Yeh, C. J., Chang, S. W., Qiu, B. H., Huang, X. S., Tsai, C. H., Chang, Y. M., Sung, P. J., Su, C. J., Cho, T. C., De, S., Lu, D., Lee, Y. J., Lee, W. H., Wu, W. F. & Yeh, W. K., 2023, In: IEEE Journal of the Electron Devices Society. 11, p. 107-113 7 p.Research output: Contribution to journal › Article › peer-review
Open Access6 Citations (Scopus)