Projects per year
Personal profile
Education
- 2002 PhD, Department of Computer Science, National Chiao Tung University
Research Interests
- Design Automation for Nanometer Ics
Experience
- 2002~2007 Assistant Manager, EDA Technology, R&D Center, Realtek Semiconductor Corporation, Taiwan
- 2007~2012 Assistant Professor, Department of Electrical Engineering, National Cheng Kung University
- 2012~present Associate Professor, Department of Electrical Engineering, National Cheng Kung University
Fingerprint Dive into the research topics where Jai-Ming Lin is active. These topic labels come from the works of this person. Together they form a unique fingerprint.
- 3 Similar Profiles
Field programmable gate arrays (FPGA)
Engineering & Materials Science
Networks (circuits)
Engineering & Materials Science
Macros
Engineering & Materials Science
Electric power utilization
Engineering & Materials Science
Placement
Mathematics
Electric potential
Engineering & Materials Science
Capacitors
Engineering & Materials Science
Convex optimization
Engineering & Materials Science
Network
Recent external collaboration on country level. Dive into details by clicking on the dots.
Projects 2008 2018
- 9 Finished
考量三維晶片平面規畫與除錯之低功耗動態調整電壓與頻率之設計方法-子計畫四：在三維晶片考量多重電壓源之整合型電源線規劃與平面規劃
15-08-01 → 16-07-31
Project: Research project
考量三維晶片平面規畫與除錯之低功耗動態調整電壓與頻率之設計方法-子計畫四：在三維晶片考量多重電壓源之整合型電源線規劃與平面規劃
14-08-01 → 15-07-31
Project: Research project
考量三維晶片平面規畫與除錯之低功耗動態調整電壓與頻率之設計方法-子計畫四：在三維晶片考量多重電壓源之整合型電源線規劃與平面規劃
13-08-01 → 14-07-31
Project: Research project
Research Output 1998 2019
Regularity-aware routability-driven macro placement methodology for mixed-size circuits with obstacles
Lin, J-M., Deng, Y. L., Li, S. T., Yu, B. H., Chang, L. Y. & Peng, T. W., 2019 Jan 1, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 27, 1, p. 57-68 12 p., 8478776.Research output: Contribution to journal › Article
Macros
Networks (circuits)
Simulated annealing
Routability-driven mixed-size placement prototyping approach considering design hierarchy and indirect connectivity between macros
Lin, J-M., Li, S. T. & Wang, Y. T., 2019 Jun 2, Proceedings of the 56th Annual Design Automation Conference 2019, DAC 2019. Institute of Electrical and Electronics Engineers Inc., a119. (Proceedings - Design Automation Conference).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
Prototyping
Placement
Macros
Connectivity
Clustering
A fast thermal-aware fixed-outline floorplanning methodology based on analytical models
Lin, J-M., Chen, T. T., Chang, Y. F., Chang, W. Y., Shyu, Y. T., Chang, Y. J. & Lu, J. M., 2018 Nov 5, 2018 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2018 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., a1. (IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
Analytical models
Temperature
Thermal effects
Integrated circuits
Hot Temperature
1
Citation
(Scopus)
Co-synthesis of floorplanning and powerplanning in 3D ICs for multiple supply voltage designs
Lin, J-M., Huang, C. Y. & Yang, J. Y., 2018 Apr 19, Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018. Institute of Electrical and Electronics Engineers Inc., Vol. 2018-January. p. 1339-1344 6 p.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
Electric potential
Module
Networks (circuits)
Methodology
Resources
2
Citations
(Scopus)
General floorplanning methodology for 3D ICs with an arbitrary bonding style
Lin, J-M. & Huang, C. Y., 2018 Apr 19, Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018. Institute of Electrical and Electronics Engineers Inc., Vol. 2018-January. p. 1199-1202 4 p.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
Bins
Methodology
Benchmark
Module
Thesis
A Routability-Driven Macro Placer Following Design Hierarchy Based on Simulated Evolution Algorithm
Author: 有倫, 鄧., 2018 Aug 18Supervisor: Lin, J. (Supervisor)
Student thesis: Master's Thesis
Design Hierarchy-Guided Placement Prototyping Approach Considering Indirect Connectivity Between Macros
Author: 思庭, 李., 2018 Oct 24Supervisor: Lin, J. (Supervisor)
Student thesis: Master's Thesis
Multiple-Row Height Cell Placement Algorithm Considering Fence-Region Constraint
Author: 奕文, 王., 2018 Oct 24Supervisor: Lin, J. (Supervisor)
Student thesis: Master's Thesis
Routability-Driven Macro-Aware Powerplanning Methodology Based on Learning Technique
Author: 志勝, 許., 2018 Aug 18Supervisor: Lin, J. (Supervisor)
Student thesis: Master's Thesis
Thermal-Aware Floorplanning Methodology Considering Application Dependent Power Based on Learning Techniques
Author: 泰廷, 陳., 2018 Jul 26Supervisor: Lin, J. (Supervisor)
Student thesis: Master's Thesis