Jone-Fang Chen

Professor

Phone886 6 2757575 ext 62395
Emailjfchen@mail.ncku.edu.tw
Websitehttp://www.ee.ncku.edu.tw/subpage_div/teacher_new_2/index2.php?teacher_id=62

2314 Citations
25 h-Index

Research output per year

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Personal profile

Education

1998 PhD, Department of Electrical Engineering and Computer Sciences, University of California at Berkeley

Research Interests

Semiconductor Devices
Semiconductor Physics
元件可靠度

Experience

1999~2003 Assistant Professor Department of Electrical Engineering National Cheng Kung University
2003~2008 Associate Professor, Department of Electrical Engineering, National Cheng Kung University
2008~ present Professor, Department of Electrical Engineering, National Cheng Kung University
2011~2014 Director, Institute of Microelectronics, National Cheng Kung University

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Projects

20 Finished

高電壓矽金氧半電晶體其性能與可靠度改善之研究

Chen, J.

17-08-01 → 18-07-31

Project: Research project

氧化層間隙壁過蝕刻對矽金氧半電晶體其電性與可靠度影響之研究

Chen, J.

16-08-01 → 17-07-31

Project: Research project

高電壓矽金氧半電晶體其性能與可靠度之研究

Chen, J.

15-08-01 → 16-07-31

Project: Research project

高電壓金氧半電晶體可靠度之研究

Chen, J.

14-08-01 → 15-07-31

Project: Research project

氮化鎵高電子移動率電晶體之改善其崩潰電壓與可靠度之研究(I)

Chen, J.

13-08-01 → 14-07-31

Project: Research project

Research Output

2314 Citations
25 h-Index
96 Article
13 Conference contribution
5 Conference article
1 Paper
1 More
- 1 Letter

Simulation-based study of high-density SRAM voltage scaling enabled by inserted-oxide FinFET technology

Wu, Y. T., Ding, F., Connelly, D., Chiang, M. H., Chen, J. F. & Liu, T. J. K., 2019 Apr, In : IEEE Transactions on Electron Devices. 66, 4, p. 1754-1759 6 p., 8661752.

Research output: Contribution to journal › Article

Characteristics and reliability of metal-oxide-semiconductor transistors with various depths of plasma-induced Si recess structure

Chen, J-F., Tsai, Y. L., Chen, C. Y., Hsu, H. T., Kao, C. Y. & Hwang, H. P., 2018 Apr 1, In : Japanese Journal of Applied Physics. 57, 4, 04FD01.

Research output: Contribution to journal › Article

High-density SRAM voltage scaling enabled by inserted-oxide FinFET technology

Wu, Y. T., Chiang, M. H., Chen, J. F., Ding, F., Connelly, D. & Liu, T. J. K., 2018 Mar 7, 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017. Institute of Electrical and Electronics Engineers Inc., p. 1-3 3 p. (2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017; vol. 2018-March).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Investigation of characteristics and hot-carrier reliability of high-voltage MOS transistors with various doping concentrations in the drift region

Tsai, Y. L., Chen, J. F., Shen, S. F., Hsu, H. T., Kao, C. Y., Chang, K. F. & Hwang, H. P., 2018 Nov 13, In : Semiconductor Science and Technology. 33, 12, 125019.

Research output: Contribution to journal › Article

Simulation-Based Study of Hybrid Fin/Planar LDMOS Design for FinFET-Based System-on-Chip Technology

Wu, Y. T., Ding, F., Connelly, D., Zheng, P., Chiang, M. H., Chen, J. F. & Liu, T. J. K., 2017 Oct, In : IEEE Transactions on Electron Devices. 64, 10, p. 4193-4199 7 p., 8010312.

Research output: Contribution to journal › Article