• 1342 Citations
  • 19 h-Index
1990 …2020
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Personal profile

Education

  • 1991 Ph.D., Univ. of Southern California, U.S.A.

Research Interests

  • VLSI Design and Testing
  • VLSI Computer-Aided Design
  • Computer Algorithms
  • VLSI Testable Design and Built-in Self Test

Experience

  • 1997-present Professor, Department of Electrical Engineering, National Cheng Kung University, R. O. C.
  • 1991 ~ 1997 Associate Professor, Department of Electrical Engineering, National Cheng Kung University, R. O. C.
  • 2003/8~2004/1 Visiting Professor, Stanford University, U.S.A.

Fingerprint Dive into the research topics where Kuen-Jong Lee is active. These topic labels come from the works of this person. Together they form a unique fingerprint.

  • 16 Similar Profiles
Networks (circuits) Engineering & Materials Science
Built-in self test Engineering & Materials Science
Testing Engineering & Materials Science
Clocks Engineering & Materials Science
Data storage equipment Engineering & Materials Science
Shift registers Engineering & Materials Science
Compaction Engineering & Materials Science
Combinatorial circuits Engineering & Materials Science

Network Recent external collaboration on country level. Dive into details by clicking on the dots.

Projects 1995 2020

Research Output 1990 2019

An Efficient Diagnosis-Aware ATPG Procedure to Enhance Diagnosis Resolution and Test Compaction

Wu, C. H., Lee, K-J. & Reddy, S. M., 2019 Sep 1, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 27, 9, p. 2105-2118 14 p., 8742768.

Research output: Contribution to journalArticle

Automatic test pattern generation
Compaction
Networks (circuits)
Trimming
Fault detection

A novel test generation method for small-delay defects with user-defined fault model

Shang, C. J., Wu, C. H., Lee, K-J. & Chen, Y. H., 2019 Apr 1, 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019. Institute of Electrical and Electronics Engineers Inc., 8741773. (2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Defects
defects
stems
time measurement
Networks (circuits)

Generating Compact Test Patterns for DC and AC Faults Using One ATPG Run

Kung, Y. C., Lee, K-J. & Reddy, S. M., 2019 Jan 23, International Test Conference 2018, ITC 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 8624678. (Proceedings - International Test Conference; vol. 2018-October).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Fault
Networks (circuits)
Experiments
Count
Coverage
Networks (circuits)
Transistors
1 Citation (Scopus)

On-Chip Self-Test Methodology With All Deterministic Compressed Test Patterns Recorded in Scan Chains

Lee, K-J., Chen, B. R. & Kochte, M. A., 2019 Feb 1, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 38, 2, p. 309-321 13 p., 8299475.

Research output: Contribution to journalArticle

Built-in self test
Failure analysis
Clocks
Controllers
Networks (circuits)

Thesis

3D-IC Built-In Diagnosis Architecture for TSVs with Different Placement and Impact Ranges of Crosstalk Faults

Author: 文軒, 許., 2016 Feb 16

Supervisor: Lee, K. (Supervisor)

Student thesis: Master's Thesis

A High-Efficiency Hybrid Multicast Routing Approach for Mesh-Based Networks-on-Chip

Author: 俊緯, 吳., 2018 Feb 5

Supervisor: Lee, K. (Supervisor)

Student thesis: Master's Thesis

A Low Area Overhead BIST Architecture Based on Response Feedback and Logic Reseeding

Author: 崇閔, 蕭., 2014 Aug 11

Supervisor: Lee, K. (Supervisor)

Student thesis: Master's Thesis

A Novel Test Generation Method for Small-Delay Defects with User-defined Fault Model

Author: 朝鈞, 商., 2019

Supervisor: Lee, K. (Supervisor)

Student thesis: Master's Thesis

A Run-Pause-Resume Silicon Debug Technique with Cycle-Granularity for Multiple Clock Domain Systems

Author: 碩聯, 洪., 2017 Aug 31

Supervisor: Lee, K. (Supervisor)

Student thesis: Master's Thesis