Projects per year
Personal profile
Education
- 1991 Ph.D., Univ. of Southern California, U.S.A.
Research Interests
- VLSI Design and Testing
- VLSI Computer-Aided Design
- Computer Algorithms
- VLSI Testable Design and Built-in Self Test
Experience
- 1997-present Professor, Department of Electrical Engineering, National Cheng Kung University, R. O. C.
- 1991 ~ 1997 Associate Professor, Department of Electrical Engineering, National Cheng Kung University, R. O. C.
- 2003/8~2004/1 Visiting Professor, Stanford University, U.S.A.
Expertise related to UN Sustainable Development Goals
In 2015, UN member states agreed to 17 global Sustainable Development Goals (SDGs) to end poverty, protect the planet and ensure prosperity for all. This person’s work contributes towards the following SDG(s):
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Collaborations and top research areas from the last five years
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Projects
- 62 Finished
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具高安全性且低耗能之物聯網晶片電路及系統之分析、設計及實作-總計畫暨子計畫六：數位電路設計及測試架構之安全性分析及防駭技術( II )
Lee, K.-J. (PI)
21-05-01 → 22-04-30
Project: Research project
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具高安全性且低耗能之物聯網晶片電路及系統之分析、設計及實作-總計畫暨子計畫六：數位電路設計及測試架構之安全性分析及防駭技術( I )
Lee, K.-J. (PI)
20-05-01 → 21-04-30
Project: Research project
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具高安全性且低耗能之物聯網晶片電路及系統之分析、設計及實作-總計畫暨子計畫六：數位電路設計及測試架構之安全性分析及防駭技術(2/2)
Lee, K.-J. (PI)
19-05-01 → 20-04-30
Project: Research project
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具高安全性且低耗能之物聯網晶片電路及系統之分析、設計及實作-總計畫暨子計畫六：數位電路設計及測試架構之安全性分析及防駭技術(2/2)
Lee, K.-J. (PI)
19-05-01 → 20-04-30
Project: Research project
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A Universal Sequential Authentication Scheme for TAPC-Based Test Standards
Chen, G. R. & Lee, K. J., 2025, (Accepted/In press) In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems.Research output: Contribution to journal › Article › peer-review
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A Lightweight Memory Protection Scheme with Criticality-Aware Encryption and Embedded MAC for Secure DNN Accelerators
Lin, Y. C. & Lee, K. J., 2024, APCCAS and PrimeAsia 2024 - 2024 IEEE 20th Asia Pacific Conference on Circuits and Systems and IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics Electronics, Proceeding. Institute of Electrical and Electronics Engineers Inc., p. 11-15 5 p. (APCCAS and PrimeAsia 2024 - 2024 IEEE 20th Asia Pacific Conference on Circuits and Systems and IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics Electronics, Proceeding).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
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An On-chip High-resolution Delay Measurement Scheme for TSVs in 3DIC
Chen, D. Y., Lee, C. H., Lee, K. J., Tseng, N. H., Hung, H. W. & Yang, H. Y., 2024, APCCAS and PrimeAsia 2024 - 2024 IEEE 20th Asia Pacific Conference on Circuits and Systems and IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics Electronics, Proceeding. Institute of Electrical and Electronics Engineers Inc., p. 74-78 5 p. (APCCAS and PrimeAsia 2024 - 2024 IEEE 20th Asia Pacific Conference on Circuits and Systems and IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics Electronics, Proceeding).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
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A Novel Unified Modular Arithmetic Unit for Elliptic Curve Cryptography
Chen, H. Y., Peng, K. Y. & Lee, K. J., 2023, 2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings. Institute of Electrical and Electronics Engineers Inc., (2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
1 Citation (Scopus) -
Accurate Estimation of Test Pattern Counts for a Wide-Range of EDT Input/Output Channel Configurations
Zheng, S. X., Yeh, C. Y., Lee, K. J., Wang, C., Cheng, W. T., Kassab, M., Rajski, J. & Reddy, S. M., 2022, Proceedings - 2022 IEEE 40th VLSI Test Symposium, VTS 2022. IEEE Computer Society, (Proceedings of the IEEE VLSI Test Symposium; vol. 2022-April).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution