Projects per year
Personal profile
Education
- 1991 Ph.D., Univ. of Southern California, U.S.A.
Research Interests
- VLSI Design and Testing
- VLSI Computer-Aided Design
- Computer Algorithms
- VLSI Testable Design and Built-in Self Test
Experience
- 1997-present Professor, Department of Electrical Engineering, National Cheng Kung University, R. O. C.
- 1991 ~ 1997 Associate Professor, Department of Electrical Engineering, National Cheng Kung University, R. O. C.
- 2003/8~2004/1 Visiting Professor, Stanford University, U.S.A.
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Projects
- 60 Finished
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具高安全性且低耗能之物聯網晶片電路及系統之分析、設計及實作-總計畫暨子計畫六：數位電路設計及測試架構之安全性分析及防駭技術(2/2)
19-05-01 → 20-04-30
Project: Research project
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具高安全性且低耗能之物聯網晶片電路及系統之分析、設計及實作-總計畫暨子計畫六：數位電路設計及測試架構之安全性分析及防駭技術(2/2)
19-05-01 → 20-04-30
Project: Research project
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Research output
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An Efficient Procedure to Generate Highly Compact Diagnosis Patterns for Transition Faults
Lee, K. J., Wu, C. H. & Hou, T. Y., 2021, (Accepted/In press) In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.Research output: Contribution to journal › Article › peer-review
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Efficient Test Compression Configuration Selection
Ye, C. S., Zheng, S. X., Tsai, F. J., Wang, C., Lee, K. J., Cheng, W. T., Reddy, S. M., Zawada, J., Kassab, M. & Rajski, J., 2021, (Accepted/In press) In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.Research output: Contribution to journal › Article › peer-review
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Test Chips with Scan-Based Logic Arrays
Chen, Y. H., Hsu, C. M. & Lee, K. J., 2021 Apr, In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 40, 4, p. 790-802 13 p., 9144517.Research output: Contribution to journal › Article › peer-review
1 Citation (Scopus) -
Efficient Prognostication of Pattern Count with Different Input Compression Ratios
Tsai, F. J., Ye, C. S., Huang, Y., Lee, K. J., Cheng, W. T., Reddy, S. M., Kassab, M. & Rajski, J., 2020 May, Proceedings - 2020 IEEE European Test Symposium, ETS 2020. Institute of Electrical and Electronics Engineers Inc., 9131586. (Proceedings of the European Test Workshop; vol. 2020-May).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
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Estimation of Test Data Volume for Scan Architectures with Different Numbers of Input Channels
Tsai, F. J., Ye, C. S., Huang, Y., Lee, K. J., Cheng, W. T., Reddy, S. M., Kassab, M., Rajski, J. & Zheng, S. X., 2020 Sep, Proceedings - 2020 IEEE International Test Conference in Asia, ITC-Asia 2020. Institute of Electrical and Electronics Engineers Inc., p. 130-135 6 p. 9226547. (Proceedings - 2020 IEEE International Test Conference in Asia, ITC-Asia 2020).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
1 Citation (Scopus)