Projects per year
Personal profile
Education
- 1991 Ph.D., Univ. of Southern California, U.S.A.
Research Interests
- VLSI Design and Testing
- VLSI Computer-Aided Design
- Computer Algorithms
- VLSI Testable Design and Built-in Self Test
Experience
- 1997-present Professor, Department of Electrical Engineering, National Cheng Kung University, R. O. C.
- 1991 ~ 1997 Associate Professor, Department of Electrical Engineering, National Cheng Kung University, R. O. C.
- 2003/8~2004/1 Visiting Professor, Stanford University, U.S.A.
Expertise related to UN Sustainable Development Goals
In 2015, UN member states agreed to 17 global Sustainable Development Goals (SDGs) to end poverty, protect the planet and ensure prosperity for all. This person’s work contributes towards the following SDG(s):
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Network
Projects
- 62 Finished
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具高安全性且低耗能之物聯網晶片電路及系統之分析、設計及實作-總計畫暨子計畫六:數位電路設計及測試架構之安全性分析及防駭技術( II )
21-05-01 → 22-04-30
Project: Research project
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具高安全性且低耗能之物聯網晶片電路及系統之分析、設計及實作-總計畫暨子計畫六:數位電路設計及測試架構之安全性分析及防駭技術( I )
20-05-01 → 21-04-30
Project: Research project
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具高安全性且低耗能之物聯網晶片電路及系統之分析、設計及實作-總計畫暨子計畫六:數位電路設計及測試架構之安全性分析及防駭技術(2/2)
19-05-01 → 20-04-30
Project: Research project
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具高安全性且低耗能之物聯網晶片電路及系統之分析、設計及實作-總計畫暨子計畫六:數位電路設計及測試架構之安全性分析及防駭技術(2/2)
19-05-01 → 20-04-30
Project: Research project
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Accurate Estimation of Test Pattern Counts for a Wide-Range of EDT Input/Output Channel Configurations
Zheng, S. X., Yeh, C. Y., Lee, K. J., Wang, C., Cheng, W. T., Kassab, M., Rajski, J. & Reddy, S. M., 2022, Proceedings - 2022 IEEE 40th VLSI Test Symposium, VTS 2022. IEEE Computer Society, (Proceedings of the IEEE VLSI Test Symposium; vol. 2022-April).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
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A Dynamic-Key Based Secure Scan Architecture for Manufacturing and In-Field IC Testing
Lee, K. J., Liu, C. A. & Wu, C. C., 2022, In: IEEE Transactions on Emerging Topics in Computing. 10, 1, p. 373-385 13 p.Research output: Contribution to journal › Article › peer-review
3 Citations (Scopus) -
An Efficient Procedure to Generate Highly Compact Diagnosis Patterns for Transition Faults
Lee, K. J., Wu, C. H. & Hou, T. Y., 2022 Mar 1, In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 41, 3, p. 737-749 13 p.Research output: Contribution to journal › Article › peer-review
1 Citation (Scopus) -
A Secure JTAG Wrapper for SoC Testing and Debugging
Lee, K. J., Lu, Z. Y. & Yeh, S. C., 2022, In: IEEE Access. 10, p. 37603-37612 10 p.Research output: Contribution to journal › Article › peer-review
Open Access1 Citation (Scopus) -
Diagnosing Transition Delay Faults under Scan-Based Logic Array
Kang, D. Y., Lin, S. N. & Lee, K. J., 2022, Proceedings - 2022 IEEE International Test Conference in Asia, ITC-Asia 2022. Institute of Electrical and Electronics Engineers Inc., p. 13-18 6 p. (Proceedings - 2022 IEEE International Test Conference in Asia, ITC-Asia 2022).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution