Kuen-Jong Lee

Personal profile

Education

1991 Ph.D., Univ. of Southern California, U.S.A.

Research Interests

VLSI Design and Testing
VLSI Computer-Aided Design
Computer Algorithms
VLSI Testable Design and Built-in Self Test

Experience

1997-present Professor, Department of Electrical Engineering, National Cheng Kung University, R. O. C.
1991 ~ 1997 Associate Professor, Department of Electrical Engineering, National Cheng Kung University, R. O. C.
2003/8~2004/1 Visiting Professor, Stanford University, U.S.A.

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Networks (circuits) Engineering & Materials Science

Built-in self test Engineering & Materials Science

Testing Engineering & Materials Science

Clocks Engineering & Materials Science

Data storage equipment Engineering & Materials Science

Shift registers Engineering & Materials Science

Compaction Engineering & Materials Science

Combinatorial circuits Engineering & Materials Science

Network Recent external collaboration on country level. Dive into details by clicking on the dots.

具高安全性且低耗能之物聯網晶片電路及系統之分析、設計及實作-總計畫暨子計畫六：數位電路設計及測試架構之安全性分析及防駭技術(2/2)

Lee, K.

19-05-01 → 20-04-30

Project: Research project

高壓縮率廣播掃描壓縮技術以及將測試資料儲存於掃描鍊之自我測試架構

Lee, K.

17-08-01 → 18-07-31

Project: Research project

適用於多種實際錯誤模型之測試與診斷向量產生方法及其完整流程之開發

Lee, K.

17-08-01 → 18-07-31

Project: Research project

車用電子之獨立式測試系統暨測試架構防駭安全技術

Lee, K.

16-08-01 → 17-07-31

Project: Research project

掃描式響應回授測試技術之研發及應用

Lee, K.

15-08-01 → 16-07-31

Project: Research project

Research Output 1990 2019

1323 Citations
19 h-Index
72 Conference contribution
64 Article
9 Conference article
6 Editorial
12 More

An Efficient Diagnosis-Aware ATPG Procedure to Enhance Diagnosis Resolution and Test Compaction

Wu, C. H., Lee, K-J. & Reddy, S. M., 2019 Sep 1, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 27, 9, p. 2105-2118 14 p., 8742768.

Research output: Contribution to journal › Article

Automatic test pattern generation

Compaction

Networks (circuits)

Trimming

Fault detection

A novel test generation method for small-delay defects with user-defined fault model

Shang, C. J., Wu, C. H., Lee, K-J. & Chen, Y. H., 2019 Apr 1, 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019. Institute of Electrical and Electronics Engineers Inc., 8741773. (2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Defects

defects

stems

time measurement

Networks (circuits)

Generating Compact Test Patterns for DC and AC Faults Using One ATPG Run

Kung, Y. C., Lee, K-J. & Reddy, S. M., 2019 Jan 23, International Test Conference 2018, ITC 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 8624678. (Proceedings - International Test Conference; vol. 2018-October).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Fault

Networks (circuits)

Experiments

Count

Coverage

Generating Single-and Double-Pattern Tests for Multiple CMOS Fault Models in One ATPG Run

Kung, Y. C., Lee, K-J. & Reddy, S. M., 2019 Jan 1, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Research output: Contribution to journal › Article

Networks (circuits)

Transistors

A Dynamic-Key Secure Scan Structure Against Scan-Based Side Channel and Memory Cold Boot Attacks

Wu, C. C., Kuo, M. H. & Lee, K-J., 2018 Dec 6, Proceedings - 2018 IEEE 27th Asian Test Symposium, ATS 2018. IEEE Computer Society, p. 48-53 6 p. 8567409. (Proceedings of the Asian Test Symposium; vol. 2018-October).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Data storage equipment

Networks (circuits)

Observability

Controllability