• 1343 Citations
  • 19 h-Index
1990 …2020
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Research Output 1990 2019

2019

An Efficient Diagnosis-Aware ATPG Procedure to Enhance Diagnosis Resolution and Test Compaction

Wu, C. H., Lee, K-J. & Reddy, S. M., 2019 Sep 1, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 27, 9, p. 2105-2118 14 p., 8742768.

Research output: Contribution to journalArticle

Automatic test pattern generation
Compaction
Networks (circuits)
Trimming
Fault detection

A novel test generation method for small-delay defects with user-defined fault model

Shang, C. J., Wu, C. H., Lee, K-J. & Chen, Y. H., 2019 Apr 1, 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019. Institute of Electrical and Electronics Engineers Inc., 8741773. (2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Defects
defects
stems
time measurement
Networks (circuits)

Generating Compact Test Patterns for DC and AC Faults Using One ATPG Run

Kung, Y. C., Lee, K-J. & Reddy, S. M., 2019 Jan 23, International Test Conference 2018, ITC 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 8624678. (Proceedings - International Test Conference; vol. 2018-October).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Fault
Networks (circuits)
Experiments
Count
Coverage
Networks (circuits)
Transistors
1 Citation (Scopus)

On-Chip Self-Test Methodology With All Deterministic Compressed Test Patterns Recorded in Scan Chains

Lee, K-J., Chen, B. R. & Kochte, M. A., 2019 Feb 1, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 38, 2, p. 309-321 13 p., 8299475.

Research output: Contribution to journalArticle

Built-in self test
Failure analysis
Clocks
Controllers
Networks (circuits)

Time-related hardware trojan attacks on processor cores

Kuo, M. H., Hu, C. M. & Lee, K. J., 2019 Sep, Proceedings - 2019 IEEE International Test Conference in Asia, ITC-Asia 2019. Institute of Electrical and Electronics Engineers Inc., p. 43-48 6 p. 8872047. (Proceedings - 2019 IEEE International Test Conference in Asia, ITC-Asia 2019).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

attack
central processing units
Clocks
Time delay
hardware
2018

A Dynamic-Key Secure Scan Structure Against Scan-Based Side Channel and Memory Cold Boot Attacks

Wu, C. C., Kuo, M. H. & Lee, K-J., 2018 Dec 6, Proceedings - 2018 IEEE 27th Asian Test Symposium, ATS 2018. IEEE Computer Society, p. 48-53 6 p. 8567409. (Proceedings of the Asian Test Symposium; vol. 2018-October).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Data storage equipment
Networks (circuits)
Observability
Controllability
2 Citations (Scopus)

A Hybrid Multicast Routing Approach with Enhanced Methods for Mesh-Based Networks-on-Chip

Wu, C. W., Lee, K-J. & Su, A. P., 2018 Sep 1, In : IEEE Transactions on Computers. 67, 9, p. 1231-1245 15 p., 8309347.

Research output: Contribution to journalArticle

Multicast Routing
Routing algorithms
Deadlock
Routing Algorithm
Mesh

A Repair-for-Diagnosis Methodology for Logic Circuits

Wu, C. H., Lin, S. L., Lee, K-J. & Reddy, S. M., 2018 Nov 1, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 26, 11, p. 2254-2267 14 p., 8423443.

Research output: Contribution to journalArticle

Logic circuits
Repair
Defects
Networks (circuits)
Failure analysis
2 Citations (Scopus)

Generating compact test patterns for stuck-at faults and transition faults in one ATPG run

Kung, Y. C., Lee, K-J. & Reddy, S. M., 2018 Sep 11, Proceedings - 2nd IEEE International Test Conference in Asia, ITC-Asia 2018. Institute of Electrical and Electronics Engineers Inc., p. 1-6 6 p. 8462939. (Proceedings - 2nd IEEE International Test Conference in Asia, ITC-Asia 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Networks (circuits)

Test compression with single-input data spreader and multiple test sessions

Chen, C. W., Kong, Y. C. & Lee, K-J., 2018 Jan 24, Proceedings - 2017 IEEE 26th Asian Test Symposium, ATS 2017. IEEE Computer Society, p. 24-29 6 p. (Proceedings of the Asian Test Symposium).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Spreaders
Program processors
Networks (circuits)
Data compression
Integrated circuits
2017

A low power synthesis flow for multi-rate systems

Kuo, H. P., Su, A. P. & Lee, K-J., 2017 Jun 5, 2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017. Institute of Electrical and Electronics Engineers Inc., 7939677

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Clocks
Synchronization
Electric power utilization
Scheduling
Throughput
1 Citation (Scopus)

A Run-Pause-Resume silicon debug technique for multiple clock domain systems

Hong, S. L. & Lee, K. J., 2017 Nov 3, ITC-Asia 2017 - International Test Conference in Asia. Institute of Electrical and Electronics Engineers Inc., p. 46-51 6 p. 8097109. (ITC-Asia 2017 - International Test Conference in Asia).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Clocks
Silicon
Flip flop circuits
Networks (circuits)
Hardware

A run-pause-resume silicon debug technique with cycle granularity for multiple clock domain systems

Hong, S. L. & Lee, K-J., 2017 Dec 29, Proceedings - 2017 IEEE International Test Conference, ITC 2017. Institute of Electrical and Electronics Engineers Inc., p. 1-10 10 p. (Proceedings - International Test Conference; vol. 2017-December).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Granularity
Clocks
Silicon
Cycle
Methodology
2 Citations (Scopus)
Crosstalk
Topology
Silicon
Testing

Foreword

Wu, C. W., Lee, K. J., Wang, L. C. & Huang, S. Y., 2017 Nov 3, In : ITC-Asia 2017 - International Test Conference in Asia. p. iv 8097094.

Research output: Contribution to journalEditorial

Test generation for open and delay faults in CMOS circuits

Wu, C. H., Lee, K. J. & Reddy, S. M., 2017 Nov 3, ITC-Asia 2017 - International Test Conference in Asia. Institute of Electrical and Electronics Engineers Inc., p. 21-26 6 p. 8097104. (ITC-Asia 2017 - International Test Conference in Asia).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Networks (circuits)
Dynamic models
Transistors
Wire
9 Citations (Scopus)

Test Stimulus Compression Based on Broadcast Scan with One Single Input

Chen, J. Z. & Lee, K. J., 2017 Jan, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 36, 1, p. 184-197 14 p., 7463526.

Research output: Contribution to journalArticle

Networks (circuits)
Switches
Flip flop circuits
Data reduction
2016
2 Citations (Scopus)

3D-IC test architecture for TSVs with different impact ranges of crosstalk faults

Hsu, W. H., Kochte, M. A. & Lee, K. J., 2016 May 31, 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016. Institute of Electrical and Electronics Engineers Inc., 7482554. (2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Crosstalk
crosstalk
Silicon
silicon
chips
2 Citations (Scopus)

An on-chip self-Test architecture with test patterns recorded in scan chains

Lee, K. J., Tang, P. H. & Kochte, M. A., 2016 Jul 2, Proceedings - 2016 IEEE International Test Conference, ITC 2016. Institute of Electrical and Electronics Engineers Inc., 7805865. (Proceedings - International Test Conference; vol. 0).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Chip
Controllers
Built-in self test
Cell
Architecture
3 Citations (Scopus)

A testable and debuggable dual-core system with thermal-aware dynamic voltage and frequency scaling

Lu, L. Y., Chang, C. Y., Chen, Z. H., Yeh, B. T., Lu, T. H., Chen, P. Y., Tang, P. H., Lee, K. J., Chiou, L. Y., Chang, S. J., Tsai, C. H., Chen, C. H. & Lin, J. M., 2016 Mar 7, 2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016. Institute of Electrical and Electronics Engineers Inc., p. 17-18 2 p. 7427980. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; vol. 25-28-January-2016).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Program processors
Microprocessor chips
Temperature
Voltage scaling
Dynamic frequency scaling
3 Citations (Scopus)

A Test-per-cycle BIST architecture with low area overhead and no storage requirement

Shiao, C. M., Lien, W. C. & Lee, K-J., 2016 May 31, 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016. Institute of Electrical and Electronics Engineers Inc., 7482556. (2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Built-in self test
Clocks
requirements
cycles
clocks
1 Citation (Scopus)

Autonomous Testing for 3D-ICs with IEEE Std. 1687

Ye, J. C., Kochte, M. A., Lee, K. J. & Wunderlich, H. J., 2016 Dec 22, Proceedings - 2016 IEEE 25th Asian Test Symposium, ATS 2016. IEEE Computer Society, p. 215-220 6 p. 7796115. (Proceedings of the Asian Test Symposium).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Controllers
Testing
1 Citation (Scopus)

Distinguishing dynamic bridging faults and transition delay faults

Wu, C. H., Lee, S. J. & Lee, K. J., 2016 Jul 21, Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015. Ren, J., Tang, T-A., Ye, F. & Yu, H. (eds.). Institute of Electrical and Electronics Engineers Inc., 7516978. (Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Networks (circuits)
Defects
Industry

Output bit selection methodology for test response compaction

Lien, W. C. & Lee, K. J., 2016 Jul 2, Proceedings - 2016 IEEE International Test Conference, ITC 2016. Institute of Electrical and Electronics Engineers Inc., 7805873. (Proceedings - International Test Conference; vol. 0).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Compaction
Methodology
Output
Networks (circuits)
Product design
1 Citation (Scopus)

Repairable Cell-Based Chip Design for Simultaneous Yield Enhancement and Fault Diagnosis

Lin, S. L., Wu, C. H. & Lee, K. J., 2016 Dec 22, Proceedings - 2016 IEEE 25th Asian Test Symposium, ATS 2016. IEEE Computer Society, p. 25-30 6 p. 7796076. (Proceedings of the Asian Test Symposium).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Failure analysis
Repair
Defects
Networks (circuits)
4 Citations (Scopus)

Test and diagnosis pattern generation for dynamic bridging faults and transition delay faults

Wu, C. H., Lee, S. J. & Lee, K. J., 2016 Mar 7, 2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016. Institute of Electrical and Electronics Engineers Inc., p. 755-760 6 p. 7428102. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; vol. 25-28-January-2016).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Networks (circuits)
Compaction
Defects
6 Citations (Scopus)

Transformation of multiple fault models to a unified model for ATPG efficiency enhancement

Wu, C. H. & Lee, K. J., 2016 Jul 2, Proceedings - 2016 IEEE International Test Conference, ITC 2016. Institute of Electrical and Electronics Engineers Inc., 7805866. (Proceedings - International Test Conference; vol. 0).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Fault
Enhancement
Model
Transform faults
Test Generation
2015
3 Citations (Scopus)

A breakpoint-based silicon debug technique with cycle-granularity for handshake-based SoC

Chen, H. C., Wu, C. R., Li, K. S. M. & Lee, K. J., 2015 Apr 22, Proceedings of the 2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015. Institute of Electrical and Electronics Engineers Inc., p. 1281-1284 4 p. 7092589. (Proceedings -Design, Automation and Test in Europe, DATE; vol. 2015-April).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Silicon
Networks (circuits)
Granulation
System-on-chip

A high-performance SoC debug platform

Liu, K. K., Hsu, W. H. & Lee, K-J., 2015 Jan 1, In : Smart Science. 3, 4, p. 202-208 7 p.

Research output: Contribution to journalArticle

High Performance
Debugging
Design Automation
Automation
Trigger
6 Citations (Scopus)

An efficient 3D-IC on-chip test framework to embed TSV testing in memory BIST

Li, L. C., Hsu, W. H., Lee, K. J. & Hsu, C. L., 2015 Mar 11, 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015. Institute of Electrical and Electronics Engineers Inc., p. 520-525 6 p. 7059059. (20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Built-in self test
Chip
Data storage equipment
Testing
Integrated circuits
2 Citations (Scopus)

An efficient diagnosis-aware pattern generation procedure for transition faults

Lee, K. J. & Wu, C. H., 2015 Feb 6, Proceedings - 2014 IEEE International Test Conference, ITC 2014. Institute of Electrical and Electronics Engineers Inc., 7035361. (Proceedings - International Test Conference; vol. 2015-February).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Fault
Networks (circuits)
Failure analysis
Program processors
Compaction
4 Citations (Scopus)

Improve transition fault diagnosability via observation point insertion

Wu, C. H., Wang, Y. D. & Lee, K-J., 2015 May 28, 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015. Institute of Electrical and Electronics Engineers Inc., 7114571. (2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Networks (circuits)
2014
8 Citations (Scopus)

An efficient diagnosis method to deal with multiple fault-pairs simultaneously using a single circuit model

Wu, C. H., Lee, K-J. & Lien, W. C., 2014 Jan 1, Proceedings - 2014 IEEE 32nd VLSI Test Symposium, VTS 2014. IEEE Computer Society, 6818790. (Proceedings of the IEEE VLSI Test Symposium).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Networks (circuits)
Data structures
6 Citations (Scopus)

An efficient diagnosis pattern generation procedure to distinguish stuck-at faults and bridging faults

Wu, C. H. & Lee, K. J., 2014 Dec 7, Proceedings - 23rd Asian Test Symposium, ATS 2014. IEEE Computer Society, p. 306-311 6 p. 06979118. (Proceedings of the Asian Test Symposium).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Defects
Networks (circuits)
Failure analysis
Program processors
Integrated circuits
23 Citations (Scopus)

Capture-power-safe test pattern determination for at-speed scan-based testing

Li, Y. H., Lien, W. C., Lin, I-C. & Lee, K-J., 2014 Jan 1, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 33, 1, p. 127-138 12 p., 6685941.

Research output: Contribution to journalArticle

Testing
Refining
Networks (circuits)
4 Citations (Scopus)

Efficient LFSR Reseeding Based on Internal-Response Feedback

Lien, W. C., Lee, K-J., Hsieh, T. Y. & Chakrabarty, K., 2014 Dec 3, In : Journal of Electronic Testing: Theory and Applications (JETTA). 30, 6, p. 673-685 13 p.

Research output: Contribution to journalArticle

Feedback
Seed
Networks (circuits)
Built-in self test
Integrated circuits
1 Citation (Scopus)

Efficient pattern generation for transition-fault diagnosis using combinational circuit model

Wang, Y. D. & Lee, K-J., 2014 Jan 23, Proceedings - 2014 IEEE 12th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014. Zhou, J. & Tang, T-A. (eds.). Institute of Electrical and Electronics Engineers Inc., 7021499. (Proceedings - 2014 IEEE 12th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Combinatorial circuits
Failure analysis
Networks (circuits)
Temperature sensors
Integrated circuits
Temperature
Temperature control
Control systems
3 Citations (Scopus)

On deadlock problem of on-chip buses supporting out-of-order transactions

Chang, C. Y. & Lee, K-J., 2014 Jan 1, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 22, 3, p. 484-496 13 p., 6490417.

Research output: Contribution to journalArticle

Network protocols
Interfaces (computer)
Communication
3 Citations (Scopus)

Output-bit selection with X-avoidance using multiple counters for test-response compaction

Lien, W. C., Lee, K-J., Chakrabarty, K. & Hsieh, T. Y., 2014 Jan 1, Proceedings - 2014 19th IEEE European Test Symposium, ETS 2014. IEEE Computer Society, 6847823. (Proceedings - 2014 19th IEEE European Test Symposium, ETS 2014).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Compaction
Networks (circuits)
Experiments
2 Citations (Scopus)

Output selection for test response compaction based on multiple counters

Lien, W. C., Lee, K-J., Chakrabarty, K. & Hsieh, T. Y., 2014 Jan 1, Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014. IEEE Computer Society, 6834865. (Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Compaction
2013
5 Citations (Scopus)

An efficient deadlock-free multicast routing algorithm for mesh-based networks-on-chip

Lee, K. J., Chang, C. Y. & Yang, H. Y., 2013 Aug 15, 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013. 6533824. (2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Routing algorithms
Routers
Network-on-chip
Communication
10 Citations (Scopus)

An efficient on-chip test generation scheme based on programmable and multiple twisted-ring counters

Lien, W. C., Lee, K. J., Hsieh, T. Y. & Ang, W. L., 2013 Aug 5, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 32, 8, p. 1254-1264 11 p., 6559094.

Research output: Contribution to journalArticle

Seed
Networks (circuits)
Inventory control
Data storage equipment
2 Citations (Scopus)

A new LFSR reseeding scheme via internal response feedback

Lien, W. C., Lee, K-J., Hsieh, T. Y. & Chakrabarty, K., 2013 Jan 1, In : Proceedings of the Asian Test Symposium. p. 97-102 6 p., 6690622.

Research output: Contribution to journalConference article

Seed
Feedback
Built-in self test
Networks (circuits)
Integrated circuits
5 Citations (Scopus)

Counter-based output selection for test response compaction

Lien, W. C., Lee, K-J., Hsieh, T. Y., Chakrabarty, K. & Wu, Y. H., 2013 Jan 7, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 32, 1, p. 152-164 13 p., 6387700.

Research output: Contribution to journalArticle

Compaction
Hardware
Networks (circuits)
2012
1 Citation (Scopus)

Accumulator-based output selection for test response compaction

Lien, W. C., Lee, K-J., Hsieh, T. Y., Chien, S. S. & Chakrabarty, K., 2012 Sep 28, p. 2313-2316. 4 p.

Research output: Contribution to conferencePaper

Compaction
Networks (circuits)
12 Citations (Scopus)

A test-per-clock LFSR reseeding algorithm for concurrent reduction on test sequence length and test data volume

Lien, W. C., Lee, K-J. & Hsieh, T. Y., 2012 Dec 1, Proceedings - 2012 IEEE 21st Asian Test Symposium, ATS 2012. p. 278-283 6 p. 6394216. (Proceedings of the Asian Test Symposium).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Seed
Clocks
Built-in self test
9 Citations (Scopus)

Efficient overdetection elimination of acceptable faults for yield improvement

Lee, K. J., Hsieh, T. Y. & Breuer, M. A., 2012 May 1, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 31, 5, p. 754-764 11 p., 6186858.

Research output: Contribution to journalArticle

Networks (circuits)
Automatic test pattern generation
Testing
1 Citation (Scopus)

Output bit selection for test response compaction based on a single counter

Lee, K-J., Lien, W. C. & Hsieh, T. Y., 2012 Dec 1, ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings. 6467671. (ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Compaction
Hardware
Networks (circuits)