• 1350 Citations
  • 19 h-Index
1990 …2020

Research output per year

If you made any changes in Pure these will be visible here soon.

Research Output

1990

A new method for assigning signal flow directions to MOS transistors

Lee, K-J., Gupta, R. & Breuer, M. A., 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers. Publ by IEEE, p. 492-495 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

A universal test sequence for CMOS scan registers

Lee, K. J. & Breuer, M. A., 1990 Dec 1, In : Proceedings of the Custom Integrated Circuits Conference.

Research output: Contribution to journalConference article

19 Citations (Scopus)
8 Citations (Scopus)

On the charge sharing problem in CMOS stuck-open fault testing

Lee, K-J. & Breuer, M. A., 1990 Sep 1, Digest of Papers - International Test Conference. Publ by IEEE, p. 417-426 10 p. (Digest of Papers - International Test Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

15 Citations (Scopus)
1991

Constraints for using IDDQ testing to detect CMOS bridging faults

Lee, K-J. & Breuer, M. A., 1991 Jan 1, p. 303-308. 6 p.

Research output: Contribution to conferencePaper

11 Citations (Scopus)
1992

A fast testing method for sequential circuits at the state transition level

Wang, W. L., Wang, J. F. & Lee, K-J., 1992 Jan 1, Proceedings International Test Conference, ITC 1992. Institute of Electrical and Electronics Engineers Inc., p. 514-519 6 p. 527863. (Proceedings - International Test Conference; vol. 1992-January).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

27 Citations (Scopus)

SWiTEST: a switch level test generation system for CMOS combinational circuits

Lee, K. J., Njinda, C. A. & Breuer, M. A., 1992 Dec 1, Proceedings - Design Automation Conference. Publ by IEEE, p. 26-29 4 p. (Proceedings - Design Automation Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)
1993

A systematic method to classify scan cells

Lee, K. J., Lu, M. H. & Wang, J. F., 1993 Jan 1, ATS 1993 Proceedings - 2nd Asian Test Symposium. IEEE Computer Society, p. 219-224 6 p. 398808. (Proceedings of the Asian Test Symposium).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

New representation for programmable logic arrays to facilitate testing and logic design

Tang, J. J., Lee, K-J. & Liu, B-D., 1993, Proceedings of the 10th IEEE Region Conference on Computer, Communication, Control and Power Engineering. Publ by IEEE, p. 561-564 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)
1994

SWiTEST: A Switch Level Test Generation System for CMOS Combinational Circuits

Lee, K. J., Njinda, C. A. & Breuer, M. A., 1994 May, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 13, 5, p. 625-637 13 p.

Research output: Contribution to journalArticle

9 Citations (Scopus)
1995
3 Citations (Scopus)

A Practical Current Sensing Technique for iddqtesting

Tang, J. J., Lee, K. J. & Liu, B. D., 1995 Jun, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 3, 2, p. 302-310 9 p.

Research output: Contribution to journalArticle

40 Citations (Scopus)

Built-in intermediate voltage testing for CMOS circuits

Tang, J. J., Lee, K. J. & Liu, B. D., 1995 Mar 6, Proceedings of the 1995 European Conference on Design and Test, EDTC 1995. Association for Computing Machinery, Inc, p. 372-376 5 p. (Proceedings of the 1995 European Conference on Design and Test, EDTC 1995).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

IDDQ fault model to facilitate the design of built-in current sensor (BICSs)

Tang, J. J., Liu, B. D. & Lee, K. J., 1995 Jan 1, In : Proceedings - IEEE International Symposium on Circuits and Systems. 1, p. 393-396 4 p.

Research output: Contribution to journalConference article

New architecture for analog boundary scan

Lee, K-J., Jeng, S. Y. & Lee, T. P., 1995 Jan 1, In : Proceedings - IEEE International Symposium on Circuits and Systems. 1, p. 409-412 4 p.

Research output: Contribution to journalConference article

2 Citations (Scopus)
1996

Analogue boundary scan architecture for DC and AC testing

Lee, K-J., Lee, T. P., Wen, R. C. & Lin, Z. Y., 1996 Apr 11, In : Electronics Letters. 32, 8, p. 704-705 2 p.

Research output: Contribution to journalArticle

2 Citations (Scopus)

Combination of automatic test pattern generation and built-in intermediate voltage sensing for detecting CMOS bridging faults

Lee, K-J., Tang, J. J., Huang, T. C. & Tsai, C. L., 1996 Dec 1, In : Proceedings of the Asian Test Symposium. p. 100-105 6 p.

Research output: Contribution to journalConference article

2 Citations (Scopus)

Low voltage built-in current sensor

Lee, K-J., Huang, K. S. & Huang, M. C., 1996 Jan 1, In : Electronics Letters. 32, 21, p. 1942-1943 2 p.

Research output: Contribution to journalArticle

2 Citations (Scopus)

Two modeling techniques for CMOS circuits to enhance test generation and fault simulation for bridging faults

Lee, K-J. & Tang, J. J., 1996 Dec 1, In : Proceedings of the Asian Test Symposium. p. 165-170 6 p.

Research output: Contribution to journalConference article

6 Citations (Scopus)
1997

Built-in current sensor designs based on the bulk-driven technique

Huang, T. C., Huang, M. C. & Lee, K. J., 1997 Dec 1, In : Proceedings of the Asian Test Symposium. p. 384-388 5 p.

Research output: Contribution to journalConference article

6 Citations (Scopus)

Concurrent test method for OTA-C filters

Lee, K. J., Huang, K. S., Wang, W. C., Pookaiyaudom, S., Sitdhikorn, R. & Thanachayanont, A., 1997 Jan 2, In : Electronics Letters. 33, 1, p. 1-3 3 p.

Research output: Contribution to journalArticle

5 Citations (Scopus)

High-speed low-voltage built-in current sensor

Huang, T. C., Huang, M. C. & Lee, K. J., 1997 Dec 1, p. 90-94. 5 p.

Research output: Contribution to conferencePaper

15 Citations (Scopus)

Two control and observation structures for analogue circuits

Lee, K. J. & Wen, Y. C., 1997 Sep 11, In : Electronics Letters. 33, 19, p. 1590-1592 3 p.

Research output: Contribution to journalArticle

1 Citation (Scopus)
1998

A built-in current sensor based on current-mode design

Lee, K. J. & Tang, J. J., 1998 Dec 1, In : IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing. 45, 1, p. 133-137 5 p.

Research output: Contribution to journalArticle

10 Citations (Scopus)

A general structure of feedback shift registers for built-in self test

Lee, K. J., Wang, W. L. & Wang, J. F. A., 1998 Sep 1, In : Journal of Information Science and Engineering. 14, 3, p. 645-667 23 p.

Research output: Contribution to journalArticle

A graph representation for programmable logic arrays to facilitate testing and logic design

Tang, J. J., Lee, K. J. & Liu, B. D., 1998 Dec 1, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 17, 10, p. 1030-1043 14 p.

Research output: Contribution to journalArticle

BIST structure for DAC testing

Wen, Y. C. & Lee, K. J., 1998 Jun 11, In : Electronics Letters. 34, 12, p. 1173-1174 2 p.

Research output: Contribution to journalArticle

20 Citations (Scopus)

Concurrent error detection, diagnosis, and fault tolerance for switched-capacitor filters

Lee, K-J. & Kuo, C. H., 1998 Dec, In : Journal of Information Science and Engineering. 14, 4, p. 863-890 28 p.

Research output: Contribution to journalArticle

1 Citation (Scopus)

On the determination of threshold voltages for CMOS gates to facilitate test pattern generation and fault simulation

Lee, K. J., Tang, J. J. & Duh, W. Y., 1998 Dec 1, In : Proceedings of the Asian Test Symposium. p. 113-118 6 p.

Research output: Contribution to journalConference article

2 Citations (Scopus)

Using a single input to support multiple scan chains

Lee, K. J., Chen, J. J. & Huang, C. H., 1998 Dec 1, In : IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers. p. 74-78 5 p.

Research output: Contribution to journalConference article

156 Citations (Scopus)
1999

A current-mode testable design of operational transconductance amplifier-capacitor filters

Lee, K. J., Wang, W. C. & Huang, K. S., 1999 Dec 1, In : IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing. 46, 4, p. 401-413 13 p.

Research output: Contribution to journalArticle

26 Citations (Scopus)

A universal March pattern generator for testing embedded memory cores

Wang, W. L., Lee, K. J. & Wang, J. F., 1999 Jan 1, Proceedings - 12th Annual IEEE International ASIC/SOC Conference. Institute of Electrical and Electronics Engineers Inc., p. 228-232 5 p. 806510. (Proceedings - 12th Annual IEEE International ASIC/SOC Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

BIFEST: A built-in intermediate fault effect sensing and test generation system for cmos bridging faults

Lee, K. J., Tang, J. J. & Huang, T. C., 1999 Jan 1, In : ACM Transactions on Design Automation of Electronic Systems. 4, 2, p. 194-218 25 p.

Research output: Contribution to journalArticle

1 Citation (Scopus)

Broadcasting test patterns to multiple circuits

Lee, K. J., Chen, J. J. & Huang, C. H., 1999 Dec 1, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 18, 12, p. 1793-1802 10 p.

Research output: Contribution to journalArticle

49 Citations (Scopus)

Efficient BIST method for small buffers

Jone, W. B., Huang, D. C., Wu, S. C. & Lee, K. J., 1999 Jan 1, Proceedings of the IEEE VLSI Test Symposium. IEEE, p. 246-251 6 p. (Proceedings of the IEEE VLSI Test Symposium).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

19 Citations (Scopus)

Embedded march algorithm test pattern generator for memory testing

Wang, W. L., Lee, K-J. & Wang, J. F., 1999, In : International Symposium on VLSI Technology, Systems, and Applications, Proceedings. p. 211-214 4 p.

Research output: Contribution to journalArticle

2 Citations (Scopus)

Input control technique for power reduction in scan circuits during test application

Huang, T. C. & Lee, K. J., 1999 Dec 1, In : Proceedings of the Asian Test Symposium. p. 315-320 6 p.

Research output: Contribution to journalConference article

32 Citations (Scopus)
2000

Accelerated test pattern generators for mixed-mode BIST environments

Wang, W. L. & Lee, K. J., 2000 Dec 1, In : Proceedings of the Asian Test Symposium. p. 368-373 6 p.

Research output: Contribution to journalConference article

2 Citations (Scopus)

An on chip ADC test structure

Wen, Y. C. & Lee, K. J., 2000 Dec 1, In : Proceedings -Design, Automation and Test in Europe, DATE. p. 221-225 5 p., 840042.

Research output: Contribution to journalConference article

38 Citations (Scopus)

Hierarchical test control architecture for core based design

Lee, K. J. & Huang, C. I., 2000 Dec 1, In : Proceedings of the Asian Test Symposium. p. 248-253 6 p.

Research output: Contribution to journalConference article

11 Citations (Scopus)

Peak-power reduction for multiple-scan circuits during test application

Lee, K. J., Huang, T. C. & Chen, J. J., 2000 Dec 1, In : Proceedings of the Asian Test Symposium. p. 453-458 6 p.

Research output: Contribution to journalConference article

60 Citations (Scopus)

Reducing test application time by scan flip-flops sharing

Chang, S. C., Lee, K. J., Wu, Z. Z. & Jone, W. B., 2000 Jan 1, In : IEE Proceedings: Computers and Digital Techniques. 147, 1, p. 42-48 7 p.

Research output: Contribution to journalArticle

7 Citations (Scopus)
2001

A low-power LFSR architecture

Huang, T. C. & Lee, K-J., 2001 Jan 1, In : Proceedings of the Asian Test Symposium. 1 p., 80.

Research output: Contribution to journalArticle

5 Citations (Scopus)