• 1348 Citations
  • 19 h-Index
1990 …2020
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Research Output 1990 2019

2 Citations (Scopus)

3D-IC test architecture for TSVs with different impact ranges of crosstalk faults

Hsu, W. H., Kochte, M. A. & Lee, K. J., 2016 May 31, 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016. Institute of Electrical and Electronics Engineers Inc., 7482554. (2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Crosstalk
crosstalk
Silicon
silicon
chips
3 Citations (Scopus)

A 0.5 μm concurrent testable chip of a fifth-order gm-C filter

Lee, K-J. & Wang, W. C., 2002 Sep 1, In : Analog Integrated Circuits and Signal Processing. 32, 3, p. 231-247 17 p.

Research output: Contribution to journalArticle

Networks (circuits)
Error detection
Low pass filters
Testing
Electric potential
3 Citations (Scopus)

A breakpoint-based silicon debug technique with cycle-granularity for handshake-based SoC

Chen, H. C., Wu, C. R., Li, K. S. M. & Lee, K. J., 2015 Apr 22, Proceedings of the 2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015. Institute of Electrical and Electronics Engineers Inc., p. 1281-1284 4 p. 7092589. (Proceedings -Design, Automation and Test in Europe, DATE; vol. 2015-April).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Silicon
Networks (circuits)
Granulation
System-on-chip
10 Citations (Scopus)

A built-in current sensor based on current-mode design

Lee, K-J. & Tang, J. J., 1998 Dec 1, In : IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing. 45, 1, p. 133-137 5 p.

Research output: Contribution to journalArticle

Sensors
Testing
Temperature
2 Citations (Scopus)

Accelerated test pattern generators for mixed-mode BIST environments

Wang, W. L. & Lee, K. J., 2000 Dec 1, In : Proceedings of the Asian Test Symposium. p. 368-373 6 p.

Research output: Contribution to journalConference article

Built-in self test
Shift registers
Feedback
Clocks
Costs
1 Citation (Scopus)

Accumulator-based output selection for test response compaction

Lien, W. C., Lee, K-J., Hsieh, T. Y., Chien, S. S. & Chakrabarty, K., 2012 Sep 28, p. 2313-2316. 4 p.

Research output: Contribution to conferencePaper

Compaction
Networks (circuits)
7 Citations (Scopus)

A complete logic BIST technology with no storage requirement

Lien, W. C. & Lee, K-J., 2010 Dec 1, Proceedings - 2010 19th IEEE Asian Test Symposium, ATS 2010. p. 129-134 6 p. 5692235. (Proceedings of the Asian Test Symposium).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Built-in self test
Networks (circuits)
Digital circuits
Data storage equipment
10 Citations (Scopus)

A complete memory address generator for scan based march algorithms

Wang, W. L. & Lee, K-J., 2005 Dec 9, In : Records of the IEEE International Workshop on Memory Technology, Design and Testing. p. 83-88 6 p.

Research output: Contribution to journalConference article

Data storage equipment
Shift registers
Feedback
Built-in self test
Clocks
5 Citations (Scopus)

A current-mode BIST structure of DACs

Wen, Y. C. & Lee, K-J., 2002 Apr 1, In : Measurement: Journal of the International Measurement Confederation. 31, 3, p. 147-163 17 p.

Research output: Contribution to journalArticle

Built-in Self-test
self tests
Built-in self test
Voltage
Nonlinearity
26 Citations (Scopus)

A current-mode testable design of operational transconductance amplifier-capacitor filters

Lee, K. J., Wang, W. C. & Huang, K. S., 1999 Dec 1, In : IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing. 46, 4, p. 401-413 13 p.

Research output: Contribution to journalArticle

Operational amplifiers
Capacitors
Error detection
Networks (circuits)
High definition television

A design automation system for SOC test platform

Huang, W. C., Lee, K-J., Chang, C. Y. & Wu, Y. H., 2007 Jun 1, In : International Journal of Electrical Engineering. 14, 3, p. 219-227 9 p.

Research output: Contribution to journalArticle

Automation
User interfaces
Controllers
Testing

A Dynamic-Key Secure Scan Structure Against Scan-Based Side Channel and Memory Cold Boot Attacks

Wu, C. C., Kuo, M. H. & Lee, K-J., 2018 Dec 6, Proceedings - 2018 IEEE 27th Asian Test Symposium, ATS 2018. IEEE Computer Society, p. 48-53 6 p. 8567409. (Proceedings of the Asian Test Symposium; vol. 2018-October).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Data storage equipment
Networks (circuits)
Observability
Controllability

A fast testing method for sequential circuits at the state transition level

Wang, W. L., Wang, J. F. & Lee, K-J., 1992 Jan 1, Proceedings International Test Conference, ITC 1992. Institute of Electrical and Electronics Engineers Inc., p. 514-519 6 p. 527863. (Proceedings - International Test Conference; vol. 1992-January).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Sequential circuits
State Transition
Testing
Logic gates
Networks (circuits)

A general structure of feedback shift registers for built-in self test

Lee, K. J., Wang, W. L. & Wang, J. F. A., 1998 Sep 1, In : Journal of Information Science and Engineering. 14, 3, p. 645-667 23 p.

Research output: Contribution to journalArticle

Built-in self test
Shift registers
Feedback
Flip flop circuits
Polynomials

A graph representation for programmable logic arrays to facilitate testing and logic design

Tang, J. J., Lee, K. J. & Liu, B. D., 1998 Dec 1, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 17, 10, p. 1030-1043 14 p.

Research output: Contribution to journalArticle

Logic design
Testing
Automatic test pattern generation
Directed graphs
Data structures
Integrated circuit design
Intellectual property core

A high-performance SoC debug platform

Liu, K. K., Hsu, W. H. & Lee, K. J., 2015 Jan 1, In : Smart Science. 3, 4, p. 202-208 7 p.

Research output: Contribution to journalArticle

High Performance
Debugging
Design Automation
Automation
Trigger
8 Citations (Scopus)

A high speed BIST architecture for DDR-SDRAM testing

Shen, S-C., Hsu, H. M., Chang, Y. W. & Lee, K-J., 2005 Dec 9, Proceedings - 2005 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2005. p. 52-57 6 p. (Records of the IEEE International Workshop on Memory Technology, Design and Testing).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Built-in self test
Testing
Data storage equipment
Pipelines
Experiments
Clocks
Demultiplexing
Broadcasting
Compression testing
Shift registers
3 Citations (Scopus)

A Hybrid Multicast Routing Approach with Enhanced Methods for Mesh-Based Networks-on-Chip

Wu, C. W., Lee, K. J. & Su, A. P., 2018 Sep 1, In : IEEE Transactions on Computers. 67, 9, p. 1231-1245 15 p., 8309347.

Research output: Contribution to journalArticle

Multicast Routing
Routing algorithms
Deadlock
Routing Algorithm
Mesh
2 Citations (Scopus)

A hybrid self-testing methodology of processor cores

Lu, T. H., Chen, C-H. & Lee, K-J., 2008 Sep 19, 2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008. p. 3378-3381 4 p. 4542183. (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Pipelines
Information use
Testing
System-on-chip
1 Citation (Scopus)

A hybrid software-based self-testing methodology for embedded processor

Lu, T. H., Chen, C-H. & Lee, K-J., 2008 Dec 1, Proceedings of the 23rd Annual ACM Symposium on Applied Computing, SAC'08. p. 1528-1534 7 p. (Proceedings of the ACM Symposium on Applied Computing).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Testing
Pipelines
Networks (circuits)
System-on-chip
5 Citations (Scopus)

A low-cost diagnosis methodology for pipelined A/D converters

Huang, C. H., Lee, K. J. & Chang, S. J., 2004 Dec 1, In : Proceedings of the Asian Test Symposium. p. 296-301 6 p.

Research output: Contribution to journalConference article

Costs
Built-in self test
Time division multiplexing
Variable frequency oscillators
Networks (circuits)
11 Citations (Scopus)

A low-cost SOC debug platform based on on-chip test architectures

Lee, K-J., Liang, S. Y. & Su, A., 2009 Dec 1, Proceedings - IEEE International SOC Conference, SOCC 2009. p. 161-164 4 p. 5398067. (Proceedings - IEEE International SOC Conference, SOCC 2009).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Silicon
Costs
Hardware
5 Citations (Scopus)

A low-power LFSR architecture

Huang, T. C. & Lee, K-J., 2001 Jan 1, In : Proceedings of the Asian Test Symposium. 1 p., 80.

Research output: Contribution to journalArticle

Built-in self test
Clocks
Networks (circuits)

A low power synthesis flow for multi-rate systems

Kuo, H. P., Su, A. P. & Lee, K-J., 2017 Jun 5, 2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017. Institute of Electrical and Electronics Engineers Inc., 7939677

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Clocks
Synchronization
Electric power utilization
Scheduling
Throughput
2 Citations (Scopus)

Analogue boundary scan architecture for DC and AC testing

Lee, K-J., Lee, T. P., Wen, R. C. & Lin, Z. Y., 1996 Apr 11, In : Electronics Letters. 32, 8, p. 704-705 2 p.

Research output: Contribution to journalArticle

Testing
Analog circuits
Switches
6 Citations (Scopus)

An efficient 3D-IC on-chip test framework to embed TSV testing in memory BIST

Li, L. C., Hsu, W. H., Lee, K. J. & Hsu, C. L., 2015 Mar 11, 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015. Institute of Electrical and Electronics Engineers Inc., p. 520-525 6 p. 7059059. (20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Built-in self test
Chip
Data storage equipment
Testing
Integrated circuits
9 Citations (Scopus)

An efficient BIST method for distributed small buffers

Jone, W. B., Huang, D. C., Wu, S. C. & Lee, K. J., 2002 Aug 1, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 10, 4, p. 512-514 3 p.

Research output: Contribution to journalArticle

Data storage equipment
Testing
Hardware
5 Citations (Scopus)

An efficient deadlock-free multicast routing algorithm for mesh-based networks-on-chip

Lee, K. J., Chang, C. Y. & Yang, H. Y., 2013 Aug 15, 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013. 6533824. (2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Routing algorithms
Routers
Network-on-chip
Communication

An efficient deterministic test pattern generator for scan-based BIST environment

Wang, W. L. & Lee, K-J., 2002 Feb 1, In : Journal of Electronic Testing: Theory and Applications (JETTA). 18, 1, p. 43-53 11 p.

Research output: Contribution to journalArticle

Built-in self test
Shift registers
Feedback
Logic circuits
Clocks

An Efficient Diagnosis-Aware ATPG Procedure to Enhance Diagnosis Resolution and Test Compaction

Wu, C. H., Lee, K-J. & Reddy, S. M., 2019 Sep 1, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 27, 9, p. 2105-2118 14 p., 8742768.

Research output: Contribution to journalArticle

Automatic test pattern generation
Compaction
Networks (circuits)
Trimming
Fault detection
2 Citations (Scopus)

An efficient diagnosis-aware pattern generation procedure for transition faults

Lee, K. J. & Wu, C. H., 2015 Feb 6, Proceedings - 2014 IEEE International Test Conference, ITC 2014. Institute of Electrical and Electronics Engineers Inc., 7035361. (Proceedings - International Test Conference; vol. 2015-February).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Fault
Networks (circuits)
Failure analysis
Program processors
Compaction
8 Citations (Scopus)

An efficient diagnosis method to deal with multiple fault-pairs simultaneously using a single circuit model

Wu, C. H., Lee, K-J. & Lien, W. C., 2014 Jan 1, Proceedings - 2014 IEEE 32nd VLSI Test Symposium, VTS 2014. IEEE Computer Society, 6818790. (Proceedings of the IEEE VLSI Test Symposium).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Networks (circuits)
Data structures
6 Citations (Scopus)

An efficient diagnosis pattern generation procedure to distinguish stuck-at faults and bridging faults

Wu, C. H. & Lee, K. J., 2014 Dec 7, Proceedings - 23rd Asian Test Symposium, ATS 2014. IEEE Computer Society, p. 306-311 6 p. 06979118. (Proceedings of the Asian Test Symposium).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Defects
Networks (circuits)
Failure analysis
Program processors
Integrated circuits
1 Citation (Scopus)

An efficient multi-phase test technique to perfectly prevent over-detection of acceptable faults for optimal yield improvement via error-tolerance

Hsieh, T. Y., Lee, K-J. & Breuer, M. A., 2009 Dec 1, 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09. p. 255-258 4 p. 5158143. (2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Degradation
Networks (circuits)
Testing
Costs
10 Citations (Scopus)

An efficient on-chip test generation scheme based on programmable and multiple twisted-ring counters

Lien, W. C., Lee, K. J., Hsieh, T. Y. & Ang, W. L., 2013 Aug 5, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 32, 8, p. 1254-1264 11 p., 6559094.

Research output: Contribution to journalArticle

Seed
Networks (circuits)
Inventory control
Data storage equipment
25 Citations (Scopus)

An embedded processor based SOC test platform

Lee, K-J., Chu, C. Y. & Hong, Y. T., 2005 Dec 1, In : Proceedings - IEEE International Symposium on Circuits and Systems. p. 2983-2986 4 p., 1465254.

Research output: Contribution to journalConference article

Built-in self test
Controllers
Data storage equipment
Testing
Costs
19 Citations (Scopus)

An error-oriented test methodology to improve yield with error-tolerance

Hsieh, T. Y., Lee, K-J. & Breuer, M. A., 2006 Nov 22, Proceedings - 24th IEEE VLSI Test Symposium. p. 130-135 6 p. 1617575. (Proceedings of the IEEE VLSI Test Symposium; vol. 2006).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Digital circuits
Costs
17 Citations (Scopus)

An error rate based test methodology to support error-tolerance

Hsieh, T. Y., Lee, K. J. & Breuer, M. A., 2008 Mar 1, In : IEEE Transactions on Reliability. 57, 1, p. 204-214 11 p.

Research output: Contribution to journalArticle

Sampling
Networks (circuits)
5 Citations (Scopus)

An error-tolerance-based test methodology to support product grading for yield enhancement

Hsieh, T. Y., Lee, K-J. & Breuer, M. A., 2011 Jun 1, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 30, 6, p. 930-934 5 p., 5768131.

Research output: Contribution to journalArticle

Networks (circuits)
2 Citations (Scopus)

A new LFSR reseeding scheme via internal response feedback

Lien, W. C., Lee, K-J., Hsieh, T. Y. & Chakrabarty, K., 2013 Jan 1, In : Proceedings of the Asian Test Symposium. p. 97-102 6 p., 6690622.

Research output: Contribution to journalConference article

Seed
Feedback
Built-in self test
Networks (circuits)
Integrated circuits
6 Citations (Scopus)

A new method for assigning signal flow directions to MOS transistors

Lee, K-J., Gupta, R. & Breuer, M. A., 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers. Publ by IEEE, p. 492-495 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

MOSFET devices
Computer aided design
Networks (circuits)
3 Citations (Scopus)
Transistors
Networks (circuits)
Gates (transistor)
Logic circuits
Computer aided design
2 Citations (Scopus)
Networks (circuits)
Testing
38 Citations (Scopus)

An on chip ADC test structure

Wen, Y. C. & Lee, K. J., 2000 Dec 1, In : Proceedings -Design, Automation and Test in Europe, DATE. p. 221-225 5 p., 840042.

Research output: Contribution to journalConference article

Digital to analog conversion
Built-in self test
Specifications
Testing
16 Citations (Scopus)

An on-chip march pattern generator for testing embedded memory cores

Wang, W. L., Lee, K-J. & Wang, J. F., 2001 Oct 1, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 9, 5, p. 730-735 6 p.

Research output: Contribution to journalArticle

Data storage equipment
Testing
Shift registers
Hardware
2 Citations (Scopus)

An on-chip self-Test architecture with test patterns recorded in scan chains

Lee, K. J., Tang, P. H. & Kochte, M. A., 2016 Jul 2, Proceedings - 2016 IEEE International Test Conference, ITC 2016. Institute of Electrical and Electronics Engineers Inc., 7805865. (Proceedings - International Test Conference; vol. 0).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Chip
Controllers
Built-in self test
Cell
Architecture