• 1348 Citations
  • 19 h-Index
1990 …2020
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Research Output 1990 2019

2012
9 Citations (Scopus)

Efficient overdetection elimination of acceptable faults for yield improvement

Lee, K. J., Hsieh, T. Y. & Breuer, M. A., 2012 May 1, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 31, 5, p. 754-764 11 p., 6186858.

Research output: Contribution to journalArticle

Networks (circuits)
Automatic test pattern generation
Testing
1 Citation (Scopus)

Output bit selection for test response compaction based on a single counter

Lee, K-J., Lien, W. C. & Hsieh, T. Y., 2012 Dec 1, ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings. 6467671. (ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Compaction
Hardware
Networks (circuits)
5 Citations (Scopus)

Routing-efficient implementation of an internal-response-based BIST architecture

Lien, W. C., Hsieh, T. Y. & Lee, K-J., 2012 Jul 25, 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers. 6212622. (2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Built-in self test
Networks (circuits)
Hardware
2011
5 Citations (Scopus)

An error-tolerance-based test methodology to support product grading for yield enhancement

Hsieh, T. Y., Lee, K. J. & Breuer, M. A., 2011 Jun 1, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 30, 6, p. 930-934 5 p., 5768131.

Research output: Contribution to journalArticle

Networks (circuits)
1 Citation (Scopus)

A rotation-based BIST with self-feedback logic to achieve complete fault coverage

Lien, W. C., Hsieh, T. Y., Tsai, C. T. & Lee, K. J., 2011 Jun 28, Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011. p. 252-255 4 p. 5783623. (Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Built-in self test
Shift registers
Feedback
Networks (circuits)
Experiments
2 Citations (Scopus)

A software/hardware co-debug platform for multi-core systems

Lee, K-J., Su, A., Chen, L. F., Jhou, J. W., Kuo, J. & Liu, M., 2011 Dec 1, Proceedings - 2011 IEEE 9th International Conference on ASIC, ASICON 2011. p. 259-262 4 p. 6157171. (Proceedings of International Conference on ASIC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Hardware
Clocks
Multicore programming
Application programs
Field programmable gate arrays (FPGA)
28 Citations (Scopus)
Pipelines
Testing
Macros
Data storage equipment

EPIDETOX: An esl platform for integrated circuit design and tool exploration

Lee, K-J., Chang, C. Y. & Chen, I. J., 2011 Nov 22, Embedded Systems Week 2011, ESWEEK 2011 - Proceedings of the 9th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS'11. p. 381-384 4 p. (Embedded Systems Week 2011, ESWEEK 2011 - Proceedings of the 9th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS'11).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Systems analysis
Integrated circuit design
Application programs
Computer hardware
User interfaces
3 Citations (Scopus)

Multi-core software/hardware co-debug platform with ARM CoreSight, on-chip test architecture and AXI/AHB bus monitor

Su, A. P., Kuo, J., Lee, K. J., Huang, I. J., Jian, G. A., Chien, C. A., Guo, J. I. & Chen, C. H., 2011 Jun 28, Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011. p. 129-134 6 p. 5783594. (Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Hardware
Inspection
Program debugging
Hazards and race conditions
Field programmable gate arrays (FPGA)
13 Citations (Scopus)

Programmable system-on-chip for silicon prototyping

Huang, C. M., Wu, C. M., Yang, C. C., Chen, S. L., Chen, C. S., Wang, J. J., Lee, K. J. & Wey, C. L., 2011 Mar 1, In : IEEE Transactions on Industrial Electronics. 58, 3, p. 830-838 9 p., 4926187.

Research output: Contribution to journalArticle

Silicon
System-on-chip
Costs
Fabrication
15 Citations (Scopus)

Test response compaction via output bit selection

Lee, K. J., Lien, W. C. & Hsieh, T. Y., 2011 Oct 1, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 30, 10, p. 1534-1544 11 p., 6022010.

Research output: Contribution to journalArticle

Compaction
Networks (circuits)
Automatic test pattern generation
Shift registers
Set theory
2010
7 Citations (Scopus)

A complete logic BIST technology with no storage requirement

Lien, W. C. & Lee, K-J., 2010 Dec 1, Proceedings - 2010 19th IEEE Asian Test Symposium, ATS 2010. p. 129-134 6 p. 5692235. (Proceedings of the Asian Test Symposium).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Built-in self test
Networks (circuits)
Digital circuits
Data storage equipment
3 Citations (Scopus)

Design of on-chip bus with OCP interface

Chang, C. Y., Chang, Y. J., Lee, K-J., Yeh, J. C., Lin, S. Y. & Ma, J. L., 2010 Nov 8, Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010. p. 211-214 4 p. 5496727. (Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Communication
Intellectual property core
11 Citations (Scopus)

On-chip SOC test platform design based on IEEE 1500 standard

Lee, K. J., Hsieh, T. Y., Chang, C. Y., Hong, Y. T. & Huang, W. C., 2010 Jul 1, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 18, 7, p. 1134-1139 6 p., 5229351.

Research output: Contribution to journalArticle

Built-in self test
Data storage equipment
Testing
Embedded systems
Field programmable gate arrays (FPGA)
11 Citations (Scopus)

A low-cost SOC debug platform based on on-chip test architectures

Lee, K-J., Liang, S. Y. & Su, A., 2009 Dec 1, Proceedings - IEEE International SOC Conference, SOCC 2009. p. 161-164 4 p. 5398067. (Proceedings - IEEE International SOC Conference, SOCC 2009).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Silicon
Costs
Hardware
1 Citation (Scopus)

An efficient multi-phase test technique to perfectly prevent over-detection of acceptable faults for optimal yield improvement via error-tolerance

Hsieh, T. Y., Lee, K-J. & Breuer, M. A., 2009 Dec 1, 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09. p. 255-258 4 p. 5158143. (2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Degradation
Networks (circuits)
Testing
Costs
1 Citation (Scopus)

A unified test and debug platform for SOC design

Lee, K-J., Chang, C. Y., Su, A. & Liang, S. Y., 2009 Dec 1, ASICON 2009 - Proceedings, 2009 8th IEEE International Conference on ASIC. p. 577-580 4 p. 5351351. (ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Built-in self test
Testing
Silicon
Failure analysis
Hardware
11 Citations (Scopus)

Full system simulation and verification framework

Lin, J. W., Wang, C. C., Chang, C. Y., Chen, C-H., Lee, K-J., Chu, Y. H., Yeh, J. C. & Hsiao, Y. C., 2009 Dec 1, 5th International Conference on Information Assurance and Security, IAS 2009. p. 165-168 4 p. 5283808. (5th International Conference on Information Assurance and Security, IAS 2009; vol. 1).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Computer hardware
Interfaces (computer)
Particle accelerators
Computer systems
Hardware
23 Citations (Scopus)

Tolerance of performance degrading faults for effective yield improvement

Hsieh, T. Y., Breuer, M. A., Annavaram, M., Gupta, S. K. & Lee, K-J., 2009 Dec 15, International Test Conference, ITC 2009 - Proceedings. 5355594. (Proceedings - International Test Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Tolerance
Fault
Degradation
Clocks
Throughput
2 Citations (Scopus)

Transaction level modeling and design space exploration for SOC test architectures

Chang, C. Y., Hsiao, C. Y., Lee, K-J. & Su, A. P., 2009 Dec 1, Proceedings of the 18th Asian Test Symposium, ATS 2009. p. 200-205 6 p. 5359358. (Proceedings of the Asian Test Symposium).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

System buses
Built-in self test
Testing
Program processors
Data storage equipment
2008
2 Citations (Scopus)

A hybrid self-testing methodology of processor cores

Lu, T. H., Chen, C-H. & Lee, K-J., 2008 Sep 19, 2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008. p. 3378-3381 4 p. 4542183. (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Pipelines
Information use
Testing
System-on-chip
1 Citation (Scopus)

A hybrid software-based self-testing methodology for embedded processor

Lu, T. H., Chen, C-H. & Lee, K-J., 2008 Dec 1, Proceedings of the 23rd Annual ACM Symposium on Applied Computing, SAC'08. p. 1528-1534 7 p. (Proceedings of the ACM Symposium on Applied Computing).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Testing
Pipelines
Networks (circuits)
System-on-chip
17 Citations (Scopus)

An error rate based test methodology to support error-tolerance

Hsieh, T. Y., Lee, K. J. & Breuer, M. A., 2008 Mar 1, In : IEEE Transactions on Reliability. 57, 1, p. 204-214 11 p.

Research output: Contribution to journalArticle

Sampling
Networks (circuits)
14 Citations (Scopus)

A software-based test methodology for direct-mapped data cache

Lin, Y. C., Tsai, Y. Y., Lee, K-J., Yen, C. W. & Chen, C-H., 2008 Dec 1, Proceedings of the 17th Asian Test Symposium, ATS 2008. p. 363-368 6 p. 4711618. (Proceedings of the Asian Test Symposium).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Data storage equipment
Physical addresses
Reduced instruction set computing
Random access storage
Testing

A systematic methodology to employ error-tolerance for yield improvement

Hsieh, T. Y., Lee, K. J., Lu, C. L. & Breuer, M. A., 2008 Sep 5, 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT. p. 105-108 4 p. 4542423. (2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Discrete cosine transforms
Integrated circuits
Networks (circuits)

Preface: Special issue on VLSI design/CAD symposium

Lee, K-J. & Wang, C. C., 2008 Apr 1, In : International Journal of Electrical Engineering. 15, 2

Research output: Contribution to journalEditorial

Computer aided design
8 Citations (Scopus)

Programmable System-on-chip (SoC) for silicon prototyping

Huang, C. M., Wu, C. M., Yang, C. C., Lee, K. J. & Wey, C. L., 2008 Dec 29, 2008 IEEE International Symposium on Industrial Electronics, ISIE 2008. p. 1976-1981 6 p. 4677107. (IEEE International Symposium on Industrial Electronics).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Silicon
System-on-chip
Costs
Fabrication
7 Citations (Scopus)

Turbo1500: Toward core-based design for test and diagnosis using the IEEE 1500 standard

Wang, L. T., Apte, R., Wu, S., Sheu, B., Lee, K. J., Wen, X., Jone, W. B., Yeh, C. H., Wang, W. S., Chao, H. J., Guo, J., Liu, J., Niu, Y., Sung, Y. C., Wang, C. C. & Li, F., 2008 Dec 1, Proceedings - International Test Conference 2008, ITC 2008. 4700630. (Proceedings - International Test Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Automation
Chip
Printed circuit boards
Printed Circuit Board
Wrapper
2007

A design automation system for SOC test platform

Huang, W. C., Lee, K-J., Chang, C. Y. & Wu, Y. H., 2007 Jun 1, In : International Journal of Electrical Engineering. 14, 3, p. 219-227 9 p.

Research output: Contribution to journalArticle

Automation
User interfaces
Controllers
Testing
2 Citations (Scopus)

A supply-gating scheme for both data-retention and spike-reduction in power management and test scheduling

Huang, T. C., Tzeng, J. C., Chao, Y. W., Chen, J. J., Liu, W. T. & Lee, K. J., 2007 Oct 1, 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers. p. 167-170 4 p. 4027523. (2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Scheduling
Power management
1 Citation (Scopus)

Preventing over-detection of acceptable faults for yield enhancement

Hsieh, T. Y., Lee, K-J. & Breuer, M. A., 2007 Jun, In : International Journal of Electrical Engineering. 14, 3, p. 185-193 9 p.

Research output: Contribution to journalArticle

Degradation
Defects
Testing
19 Citations (Scopus)

Reduction of detected acceptable faults for yield improvement via error-tolerance

Hsieh, T. Y., Lee, K-J. & Breuer, M. A., 2007 Sep 4, Proceedings - 2007 Design, Automation and Test in Europe Conference and Exhibition, DATE 2007. p. 1599-1604 6 p. 4212040. (Proceedings -Design, Automation and Test in Europe, DATE).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Testing
Degradation
2 Citations (Scopus)

Test efficiency analysis and improvement of SOC test platforms

Hsieh, T. Y., Lee, K-J. & You, J. J., 2007 Dec 1, Proceedings of the 16th Asian Test Symposium, ATS 2007. p. 463-466 4 p. 4388055. (Proceedings of the Asian Test Symposium).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Testing
6 Citations (Scopus)

Toward automatic synthesis of SOC test platforms

Huang, W. C., Chang, C. Y. & Lee, K. J., 2007 Sep 28, 2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers. 4239426. (2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Automation
User interfaces
Hardware
Controllers
2006
19 Citations (Scopus)

An error-oriented test methodology to improve yield with error-tolerance

Hsieh, T. Y., Lee, K-J. & Breuer, M. A., 2006 Nov 22, Proceedings - 24th IEEE VLSI Test Symposium. p. 130-135 6 p. 1617575. (Proceedings of the IEEE VLSI Test Symposium; vol. 2006).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Digital circuits
Costs
2 Citations (Scopus)

Boundary scan and core-based testing

Lee, K. J., 2006 Dec 1, VLSI Test Principles and Architectures. Elsevier Inc., p. 557-618 62 p.

Research output: Chapter in Book/Report/Conference proceedingChapter

Testing
Industry
Controller
12 Citations (Scopus)

Multi-Project System-on-Chip (MP-SoC): A novel test vehicle for SoC silicon prototyping

Huang, C. M., Lee, K-J., Yang, C. C., Hu, W. H., Wang, S. S., Chen, J. B., Chen, C. S., Van, L. D., Wu, C. M., Tsai, W. C. & Jou, J. Y., 2006 Jan 1, 2006 IEEE International Systems-on-Chip Conference, SOC. Institute of Electrical and Electronics Engineers Inc., p. 137-140 4 p. 4063036. (2006 IEEE International Systems-on-Chip Conference, SOC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Silicon
Microprocessor chips
System-on-chip
Demonstrations
Costs

Special issue preface

Lee, K. J. & Liu, B. D., 2006 Feb 1, In : International Journal of Electrical Engineering. 13, 1, p. i

Research output: Contribution to journalEditorial

1 Citation (Scopus)

Test compression

Li, X., Lee, K-J. & Touba, N. A., 2006 Dec 1, VLSI Test Principles and Architectures. Elsevier Inc., p. 341-396 56 p.

Research output: Chapter in Book/Report/Conference proceedingChapter

Compression
Broadcasting
Industry
Bandwidth
Testing
2005
10 Citations (Scopus)

A complete memory address generator for scan based march algorithms

Wang, W. L. & Lee, K-J., 2005 Dec 9, In : Records of the IEEE International Workshop on Memory Technology, Design and Testing. p. 83-88 6 p.

Research output: Contribution to journalConference article

Data storage equipment
Shift registers
Feedback
Built-in self test
Clocks
8 Citations (Scopus)

A high speed BIST architecture for DDR-SDRAM testing

Shen, S-C., Hsu, H. M., Chang, Y. W. & Lee, K-J., 2005 Dec 9, Proceedings - 2005 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2005. p. 52-57 6 p. (Records of the IEEE International Workshop on Memory Technology, Design and Testing).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Built-in self test
Testing
Data storage equipment
Pipelines
Experiments
25 Citations (Scopus)

An embedded processor based SOC test platform

Lee, K-J., Chu, C. Y. & Hong, Y. T., 2005 Dec 1, In : Proceedings - IEEE International Symposium on Circuits and Systems. p. 2983-2986 4 p., 1465254.

Research output: Contribution to journalConference article

Built-in self test
Controllers
Data storage equipment
Testing
Costs
42 Citations (Scopus)

A novel test methodology based on error-rate to support error-tolerance

Lee, K-J., Hsieh, T. Y. & Breuer, M. A., 2005, IEEE International Test Conference, Proceedings, ITC 2005. Vol. 2005. p. 1136-1144 9 p. 1584081

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Defects
Fault tolerance
System-on-chip
6 Citations (Scopus)

Efficient test scheduling for hierarchical core based design

Wang, T. P., Tsai, C. Y., Shieh, M-D. & Lee, K-J., 2005, 2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT). Vol. 2005. p. 200-203 4 p. 1500055

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Scheduling
System-on-chip
Fabrication
2004
5 Citations (Scopus)

A low-cost diagnosis methodology for pipelined A/D converters

Huang, C. H., Lee, K. J. & Chang, S. J., 2004 Dec 1, In : Proceedings of the Asian Test Symposium. p. 296-301 6 p.

Research output: Contribution to journalConference article

Costs
Built-in self test
Time division multiplexing
Variable frequency oscillators
Networks (circuits)
1 Citation (Scopus)
Interchanges
Digital to analog conversion
Capacitors
Feedback
Harmonic distortion
2 Citations (Scopus)

Efficient testing and design-for-testability schemes for multimedia cores: A case study on DCT circuits

Shieh, M. D., Shen, S. C., Lin, Y. C. & Lee, K. J., 2004 Dec 1, p. 177-180. 4 p.

Research output: Contribution to conferencePaper

Design for testability
Discrete cosine transforms
Networks (circuits)
Testing
Broadcasting

Proceedings of the Asian Test Symposium: Foreword

Lee, K. J., Huang, S. Y., Su, C. C. & Shieh, M. D., 2004 Dec 1, Proceedings of the Asian Test Symposium, ATS'04. p. xi (Proceedings of the Asian Test Symposium).

Research output: Chapter in Book/Report/Conference proceedingConference contribution