• 1348 Citations
  • 19 h-Index
1990 …2020
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Research Output 1990 2019

2003
16 Citations (Scopus)

A sigma-delta modulation based BIST scheme for A/D converters

Lee, K. J., Chang, S. J. & Tzeng, R. S., 2003 Jan 1, Proceedings - 12th Asian Test Symposium, ATS 2003. IEEE Computer Society, p. 124-127 4 p. 1250796. (Proceedings of the Asian Test Symposium; vol. 2003-January).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Delta sigma modulation
Built-in self test
Signal generators
Testing
23 Citations (Scopus)

Test pattern generation and clock disabling for simultaneous test time and power reduction

Chen, J. J., Yang, C. K. & Lee, K-J., 2003 Mar 1, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 22, 3, p. 363-369 7 p.

Research output: Contribution to journalArticle

Clocks
Energy dissipation
Networks (circuits)
Electric power utilization
Testing
2002
3 Citations (Scopus)

A 0.5 μm concurrent testable chip of a fifth-order gm-C filter

Lee, K-J. & Wang, W. C., 2002 Sep 1, In : Analog Integrated Circuits and Signal Processing. 32, 3, p. 231-247 17 p.

Research output: Contribution to journalArticle

Networks (circuits)
Error detection
Low pass filters
Testing
Electric potential
5 Citations (Scopus)

A current-mode BIST structure of DACs

Wen, Y. C. & Lee, K-J., 2002 Apr 1, In : Measurement: Journal of the International Measurement Confederation. 31, 3, p. 147-163 17 p.

Research output: Contribution to journalArticle

Built-in Self-test
self tests
Built-in self test
Voltage
Nonlinearity
9 Citations (Scopus)

An efficient BIST method for distributed small buffers

Jone, W. B., Huang, D. C., Wu, S. C. & Lee, K. J., 2002 Aug 1, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 10, 4, p. 512-514 3 p.

Research output: Contribution to journalArticle

Data storage equipment
Testing
Hardware

An efficient deterministic test pattern generator for scan-based BIST environment

Wang, W. L. & Lee, K-J., 2002 Feb 1, In : Journal of Electronic Testing: Theory and Applications (JETTA). 18, 1, p. 43-53 11 p.

Research output: Contribution to journalArticle

Built-in self test
Shift registers
Feedback
Logic circuits
Clocks
2 Citations (Scopus)
Networks (circuits)
Testing
2 Citations (Scopus)

A programmable data background generator for march based memory testing

Wang, W. L. & Lee, K-J., 2002 Jan 1, 2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings. Institute of Electrical and Electronics Engineers Inc., p. 347-350 4 p. 1031603. (2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Data storage equipment
Testing
Built-in self test
Dynamic random access storage
Static random access storage

Guest editorial

Lee, K-J. & Su, C. C., 2002 Feb 1, In : Journal of Electronic Testing: Theory and Applications (JETTA). 18, 1, p. 15-16 2 p.

Research output: Contribution to journalEditorial

Digital integrated circuits
Sequential circuits
Combinatorial circuits
Built-in self test
Shift registers
1 Citation (Scopus)

Reducing test application time and power dissipation for scan-based testing via multiple clock disabling

Lee, K-J. & Chen, J. J., 2002 Jan 1, Proceedings of the 11th Asian Test Symposium, ATS 2002. IEEE Computer Society, p. 338-343 6 p. 1181734. (Proceedings of the Asian Test Symposium; vol. 2002-January).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Clocks
Energy dissipation
Testing
Electric power utilization
2001
Integrated circuit design
Intellectual property core
5 Citations (Scopus)

A low-power LFSR architecture

Huang, T. C. & Lee, K-J., 2001 Jan 1, In : Proceedings of the Asian Test Symposium. 1 p., 80.

Research output: Contribution to journalArticle

Built-in self test
Clocks
Networks (circuits)
Analog circuits
Switches
16 Citations (Scopus)

An on-chip march pattern generator for testing embedded memory cores

Wang, W. L., Lee, K-J. & Wang, J. F., 2001 Oct 1, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 9, 5, p. 730-735 6 p.

Research output: Contribution to journalArticle

Data storage equipment
Testing
Shift registers
Hardware
31 Citations (Scopus)

A token scan architecture for low power testing

Huang, T. C. & Lee, K-J., 2001 Dec 1, In : IEEE International Test Conference (TC). p. 660-669 10 p.

Research output: Contribution to journalConference article

Clocks
Testing
Networks (circuits)
Energy dissipation
Periodicity
Shift registers
Feedback
Built-in self test
Clocks
Costs
42 Citations (Scopus)
Electric power utilization
Networks (circuits)
Experiments
5 Citations (Scopus)

Token scan cell for low power testing

Huang, T. C. & Lee, K. J., 2001 May 24, In : Electronics Letters. 37, 11, p. 678-679 2 p.

Research output: Contribution to journalArticle

Flip flop circuits
Networks (circuits)
Testing
Clocks
Scanning
2000
2 Citations (Scopus)

Accelerated test pattern generators for mixed-mode BIST environments

Wang, W. L. & Lee, K. J., 2000 Dec 1, In : Proceedings of the Asian Test Symposium. p. 368-373 6 p.

Research output: Contribution to journalConference article

Built-in self test
Shift registers
Feedback
Clocks
Costs
38 Citations (Scopus)

An on chip ADC test structure

Wen, Y. C. & Lee, K. J., 2000 Dec 1, In : Proceedings -Design, Automation and Test in Europe, DATE. p. 221-225 5 p., 840042.

Research output: Contribution to journalConference article

Digital to analog conversion
Built-in self test
Specifications
Testing
11 Citations (Scopus)

Hierarchical test control architecture for core based design

Lee, K. J. & Huang, C. I., 2000 Dec 1, In : Proceedings of the Asian Test Symposium. p. 248-253 6 p.

Research output: Contribution to journalConference article

Testing
Integrated circuit design
System-on-chip
Intellectual property core
60 Citations (Scopus)

Peak-power reduction for multiple-scan circuits during test application

Lee, K. J., Huang, T. C. & Chen, J. J., 2000 Dec 1, In : Proceedings of the Asian Test Symposium. p. 453-458 6 p.

Research output: Contribution to journalConference article

Networks (circuits)
Testing
7 Citations (Scopus)

Reducing test application time by scan flip-flops sharing

Chang, S. C., Lee, K. J., Wu, Z. Z. & Jone, W. B., 2000 Jan 1, In : IEE Proceedings: Computers and Digital Techniques. 147, 1, p. 42-48 7 p.

Research output: Contribution to journalArticle

Flip flop circuits
Flip
Sharing
Networks (circuits)
Fault
1999
26 Citations (Scopus)

A current-mode testable design of operational transconductance amplifier-capacitor filters

Lee, K. J., Wang, W. C. & Huang, K. S., 1999 Dec 1, In : IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing. 46, 4, p. 401-413 13 p.

Research output: Contribution to journalArticle

Operational amplifiers
Capacitors
Error detection
Networks (circuits)
High definition television
2 Citations (Scopus)

A universal March pattern generator for testing embedded memory cores

Wang, W. L., Lee, K. J. & Wang, J. F., 1999 Jan 1, Proceedings - 12th Annual IEEE International ASIC/SOC Conference. Institute of Electrical and Electronics Engineers Inc., p. 228-232 5 p. 806510. (Proceedings - 12th Annual IEEE International ASIC/SOC Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Hardware
Data storage equipment
Testing
1 Citation (Scopus)

BIFEST: A built-in intermediate fault effect sensing and test generation system for cmos bridging faults

Lee, K. J., Tang, J. J. & Huang, T. C., 1999 Jan 1, In : ACM Transactions on Design Automation of Electronic Systems. 4, 2, p. 194-218 25 p.

Research output: Contribution to journalArticle

Electric potential
Networks (circuits)
Monitoring
Sensors
Testing
49 Citations (Scopus)

Broadcasting test patterns to multiple circuits

Lee, K-J., Chen, J. J. & Huang, C. H., 1999 Dec 1, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 18, 12, p. 1793-1802 10 p.

Research output: Contribution to journalArticle

Broadcasting
Sequential circuits
Networks (circuits)
Compaction
Automatic test pattern generation
19 Citations (Scopus)

Efficient BIST method for small buffers

Jone, W. B., Huang, D. C., Wu, S. C. & Lee, K. J., 1999 Jan 1, Proceedings of the IEEE VLSI Test Symposium. IEEE, p. 246-251 6 p. (Proceedings of the IEEE VLSI Test Symposium).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Data storage equipment
Testing
Controllers
2 Citations (Scopus)

Embedded march algorithm test pattern generator for memory testing

Wang, W. L., Lee, K-J. & Wang, J. F., 1999, In : International Symposium on VLSI Technology, Systems, and Applications, Proceedings. p. 211-214 4 p.

Research output: Contribution to journalArticle

test pattern generators
systems-on-a-chip
Data storage equipment
Testing
hardware
32 Citations (Scopus)

Input control technique for power reduction in scan circuits during test application

Huang, T. C. & Lee, K. J., 1999 Dec 1, In : Proceedings of the Asian Test Symposium. p. 315-320 6 p.

Research output: Contribution to journalConference article

Networks (circuits)
1998
10 Citations (Scopus)

A built-in current sensor based on current-mode design

Lee, K-J. & Tang, J. J., 1998 Dec 1, In : IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing. 45, 1, p. 133-137 5 p.

Research output: Contribution to journalArticle

Sensors
Testing
Temperature

A general structure of feedback shift registers for built-in self test

Lee, K. J., Wang, W. L. & Wang, J. F. A., 1998 Sep 1, In : Journal of Information Science and Engineering. 14, 3, p. 645-667 23 p.

Research output: Contribution to journalArticle

Built-in self test
Shift registers
Feedback
Flip flop circuits
Polynomials

A graph representation for programmable logic arrays to facilitate testing and logic design

Tang, J. J., Lee, K. J. & Liu, B. D., 1998 Dec 1, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 17, 10, p. 1030-1043 14 p.

Research output: Contribution to journalArticle

Logic design
Testing
Automatic test pattern generation
Directed graphs
Data structures
20 Citations (Scopus)

BIST structure for DAC testing

Wen, Y. C. & Lee, K. J., 1998 Jun 11, In : Electronics Letters. 34, 12, p. 1173-1174 2 p.

Research output: Contribution to journalArticle

Built-in self test
Digital to analog conversion
Testing
Electric potential
1 Citation (Scopus)

Concurrent error detection, diagnosis, and fault tolerance for switched-capacitor filters

Lee, K-J. & Kuo, C. H., 1998 Dec, In : Journal of Information Science and Engineering. 14, 4, p. 863-890 28 p.

Research output: Contribution to journalArticle

Switched capacitor filters
Error detection
Fault tolerance
tolerance
Networks (circuits)
2 Citations (Scopus)

On the determination of threshold voltages for CMOS gates to facilitate test pattern generation and fault simulation

Lee, K. J., Tang, J. J. & Duh, W. Y., 1998 Dec 1, In : Proceedings of the Asian Test Symposium. p. 113-118 6 p.

Research output: Contribution to journalConference article

SPICE
Threshold voltage
Networks (circuits)
155 Citations (Scopus)

Using a single input to support multiple scan chains

Lee, K. J., Chen, J. J. & Huang, C. H., 1998 Dec 1, In : IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers. p. 74-78 5 p.

Research output: Contribution to journalConference article

Sequential circuits
Combinatorial circuits
Networks (circuits)
Testing
1997
6 Citations (Scopus)

Built-in current sensor designs based on the bulk-driven technique

Huang, T. C., Huang, M. C. & Lee, K. J., 1997 Dec 1, In : Proceedings of the Asian Test Symposium. p. 384-388 5 p.

Research output: Contribution to journalConference article

Sensors
Energy dissipation
Mirrors
Degradation
Networks (circuits)
5 Citations (Scopus)

Concurrent test method for OTA-C filters

Lee, K. J., Huang, K. S., Wang, W. C., Pookaiyaudom, S., Sitdhikorn, R. & Thanachayanont, A., 1997 Jan 2, In : Electronics Letters. 33, 1, p. 1-3 3 p.

Research output: Contribution to journalArticle

Networks (circuits)
Electric potential
15 Citations (Scopus)

High-speed low-voltage built-in current sensor

Huang, T. C., Huang, M. C. & Lee, K. J., 1997 Dec 1, p. 90-94. 5 p.

Research output: Contribution to conferencePaper

Sensors
Electric potential
Mirrors
Voltage drop
1 Citation (Scopus)

Two control and observation structures for analogue circuits

Lee, K. J. & Wen, Y. C., 1997 Sep 11, In : Electronics Letters. 33, 19, p. 1590-1592 3 p.

Research output: Contribution to journalArticle

Analog circuits
Testing
Switches
1996
2 Citations (Scopus)

Analogue boundary scan architecture for DC and AC testing

Lee, K-J., Lee, T. P., Wen, R. C. & Lin, Z. Y., 1996 Apr 11, In : Electronics Letters. 32, 8, p. 704-705 2 p.

Research output: Contribution to journalArticle

Testing
2 Citations (Scopus)

Combination of automatic test pattern generation and built-in intermediate voltage sensing for detecting CMOS bridging faults

Lee, K-J., Tang, J. J., Huang, T. C. & Tsai, C. L., 1996 Dec 1, In : Proceedings of the Asian Test Symposium. p. 100-105 6 p.

Research output: Contribution to journalConference article

Automatic test pattern generation
Electric potential
Networks (circuits)
Monitoring
Sensors
2 Citations (Scopus)

Low voltage built-in current sensor

Lee, K-J., Huang, K. S. & Huang, M. C., 1996 Jan 1, In : Electronics Letters. 32, 21, p. 1942-1943 2 p.

Research output: Contribution to journalArticle

Error detection
Sensors
Electric potential
Aspect ratio
Transistors
6 Citations (Scopus)

Two modeling techniques for CMOS circuits to enhance test generation and fault simulation for bridging faults

Lee, K-J. & Tang, J. J., 1996 Dec 1, In : Proceedings of the Asian Test Symposium. p. 165-170 6 p.

Research output: Contribution to journalConference article

Networks (circuits)
SPICE
Transistors
Electric potential
1995
3 Citations (Scopus)
Transistors
Networks (circuits)
Gates (transistor)
Logic circuits
Computer aided design
40 Citations (Scopus)

A Practical Current Sensing Technique for iddqtesting

Tang, J. J., Lee, K-J. & Liu, B-D., 1995 Jan 1, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 3, 2, p. 302-310 9 p.

Research output: Contribution to journalArticle

Networks (circuits)
Design for testability
Sensors
Testing
Electric potential
7 Citations (Scopus)

Built-in intermediate voltage testing for CMOS circuits

Tang, J. J., Lee, K. J. & Liu, B. D., 1995 Mar 6, Proceedings of the 1995 European Conference on Design and Test, EDTC 1995. Association for Computing Machinery, Inc, p. 372-376 5 p. (Proceedings of the 1995 European Conference on Design and Test, EDTC 1995).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Networks (circuits)
Testing
Electric potential

IDDQ fault model to facilitate the design of built-in current sensor (BICSs)

Tang, J. J., Liu, B. D. & Lee, K. J., 1995 Jan 1, In : Proceedings - IEEE International Symposium on Circuits and Systems. 1, p. 393-396 4 p.

Research output: Contribution to journalConference article

Networks (circuits)
Sensors
Formal methods
Digital circuits
2 Citations (Scopus)

New architecture for analog boundary scan

Lee, K-J., Jeng, S. Y. & Lee, T. P., 1995 Jan 1, In : Proceedings - IEEE International Symposium on Circuits and Systems. 1, p. 409-412 4 p.

Research output: Contribution to journalConference article

Digital circuits
Analog circuits
Testing