• 1331 Citations
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1990 …2020
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Research Output 1990 2019

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Conference contribution
2019

A novel test generation method for small-delay defects with user-defined fault model

Shang, C. J., Wu, C. H., Lee, K-J. & Chen, Y. H., 2019 Apr 1, 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019. Institute of Electrical and Electronics Engineers Inc., 8741773. (2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Defects
defects
stems
time measurement
Networks (circuits)

Generating Compact Test Patterns for DC and AC Faults Using One ATPG Run

Kung, Y. C., Lee, K-J. & Reddy, S. M., 2019 Jan 23, International Test Conference 2018, ITC 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 8624678. (Proceedings - International Test Conference; vol. 2018-October).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Fault
Networks (circuits)
Experiments
Count
Coverage
2018

A Dynamic-Key Secure Scan Structure Against Scan-Based Side Channel and Memory Cold Boot Attacks

Wu, C. C., Kuo, M. H. & Lee, K-J., 2018 Dec 6, Proceedings - 2018 IEEE 27th Asian Test Symposium, ATS 2018. IEEE Computer Society, p. 48-53 6 p. 8567409. (Proceedings of the Asian Test Symposium; vol. 2018-October).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Data storage equipment
Networks (circuits)
Observability
Controllability
2 Citations (Scopus)

Generating compact test patterns for stuck-at faults and transition faults in one ATPG run

Kung, Y. C., Lee, K-J. & Reddy, S. M., 2018 Sep 11, Proceedings - 2nd IEEE International Test Conference in Asia, ITC-Asia 2018. Institute of Electrical and Electronics Engineers Inc., p. 1-6 6 p. 8462939. (Proceedings - 2nd IEEE International Test Conference in Asia, ITC-Asia 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Networks (circuits)

Test compression with single-input data spreader and multiple test sessions

Chen, C. W., Kong, Y. C. & Lee, K-J., 2018 Jan 24, Proceedings - 2017 IEEE 26th Asian Test Symposium, ATS 2017. IEEE Computer Society, p. 24-29 6 p. (Proceedings of the Asian Test Symposium).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Spreaders
Program processors
Networks (circuits)
Data compression
Integrated circuits
2017

A low power synthesis flow for multi-rate systems

Kuo, H. P., Su, A. P. & Lee, K-J., 2017 Jun 5, 2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017. Institute of Electrical and Electronics Engineers Inc., 7939677

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Clocks
Synchronization
Electric power utilization
Scheduling
Throughput
1 Citation (Scopus)

A Run-Pause-Resume silicon debug technique for multiple clock domain systems

Hong, S. L. & Lee, K-J., 2017 Nov 3, ITC-Asia 2017 - International Test Conference in Asia. Institute of Electrical and Electronics Engineers Inc., p. 46-51 6 p. 8097109. (ITC-Asia 2017 - International Test Conference in Asia).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Clocks
Silicon
Flip flop circuits
Networks (circuits)
Hardware

A run-pause-resume silicon debug technique with cycle granularity for multiple clock domain systems

Hong, S. L. & Lee, K-J., 2017 Dec 29, Proceedings - 2017 IEEE International Test Conference, ITC 2017. Institute of Electrical and Electronics Engineers Inc., p. 1-10 10 p. (Proceedings - International Test Conference; vol. 2017-December).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Granularity
Clocks
Silicon
Cycle
Methodology

Test generation for open and delay faults in CMOS circuits

Wu, C. H., Lee, K-J. & Reddy, S. M., 2017 Nov 3, ITC-Asia 2017 - International Test Conference in Asia. Institute of Electrical and Electronics Engineers Inc., p. 21-26 6 p. 8097104. (ITC-Asia 2017 - International Test Conference in Asia).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Networks (circuits)
Dynamic models
Transistors
Wire
2016
2 Citations (Scopus)

3D-IC test architecture for TSVs with different impact ranges of crosstalk faults

Hsu, W. H., Kochte, M. A. & Lee, K-J., 2016 May 31, 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016. Institute of Electrical and Electronics Engineers Inc., 7482554. (2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Crosstalk
crosstalk
Silicon
silicon
chips

An on-chip self-Test architecture with test patterns recorded in scan chains

Lee, K-J., Tang, P. H. & Kochte, M. A., 2016 Jul 2, Proceedings - 2016 IEEE International Test Conference, ITC 2016. Institute of Electrical and Electronics Engineers Inc., 7805865. (Proceedings - International Test Conference; vol. 0).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Chip
Controllers
Built-in self test
Cell
Architecture
3 Citations (Scopus)

A testable and debuggable dual-core system with thermal-aware dynamic voltage and frequency scaling

Lu, L. Y., Chang, C. Y., Chen, Z. H., Yeh, B. T., Lu, T. H., Chen, P. Y., Tang, P. H., Lee, K-J., Chiou, L-Y., Chang, S-J., Tsai, C-H., Chen, C-H. & Lin, J-M., 2016 Mar 7, 2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016. Institute of Electrical and Electronics Engineers Inc., p. 17-18 2 p. 7427980. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; vol. 25-28-January-2016).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Program processors
Microprocessor chips
Temperature
Voltage scaling
Dynamic frequency scaling
3 Citations (Scopus)

A Test-per-cycle BIST architecture with low area overhead and no storage requirement

Shiao, C. M., Lien, W. C. & Lee, K-J., 2016 May 31, 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016. Institute of Electrical and Electronics Engineers Inc., 7482556. (2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Built-in self test
Clocks
requirements
cycles
clocks
1 Citation (Scopus)

Autonomous Testing for 3D-ICs with IEEE Std. 1687

Ye, J. C., Kochte, M. A., Lee, K-J. & Wunderlich, H. J., 2016 Dec 22, Proceedings - 2016 IEEE 25th Asian Test Symposium, ATS 2016. IEEE Computer Society, p. 215-220 6 p. 7796115. (Proceedings of the Asian Test Symposium).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Controllers
Testing
1 Citation (Scopus)

Distinguishing dynamic bridging faults and transition delay faults

Wu, C. H., Lee, S. J. & Lee, K-J., 2016 Jul 21, Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015. Ren, J., Tang, T-A., Ye, F. & Yu, H. (eds.). Institute of Electrical and Electronics Engineers Inc., 7516978. (Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Networks (circuits)
Defects
Industry

Output bit selection methodology for test response compaction

Lien, W. C. & Lee, K-J., 2016 Jul 2, Proceedings - 2016 IEEE International Test Conference, ITC 2016. Institute of Electrical and Electronics Engineers Inc., 7805873. (Proceedings - International Test Conference; vol. 0).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Compaction
Methodology
Output
Networks (circuits)
Product design
1 Citation (Scopus)

Repairable Cell-Based Chip Design for Simultaneous Yield Enhancement and Fault Diagnosis

Lin, S. L., Wu, C. H. & Lee, K-J., 2016 Dec 22, Proceedings - 2016 IEEE 25th Asian Test Symposium, ATS 2016. IEEE Computer Society, p. 25-30 6 p. 7796076. (Proceedings of the Asian Test Symposium).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Failure analysis
Repair
Defects
Networks (circuits)
4 Citations (Scopus)

Test and diagnosis pattern generation for dynamic bridging faults and transition delay faults

Wu, C. H., Lee, S. J. & Lee, K-J., 2016 Mar 7, 2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016. Institute of Electrical and Electronics Engineers Inc., p. 755-760 6 p. 7428102. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; vol. 25-28-January-2016).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Networks (circuits)
Compaction
Defects

Transformation of multiple fault models to a unified model for ATPG efficiency enhancement

Wu, C. H. & Lee, K-J., 2016 Jul 2, Proceedings - 2016 IEEE International Test Conference, ITC 2016. Institute of Electrical and Electronics Engineers Inc., 7805866. (Proceedings - International Test Conference; vol. 0).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Fault
Enhancement
Model
Transform faults
Test Generation
2015
3 Citations (Scopus)

A breakpoint-based silicon debug technique with cycle-granularity for handshake-based SoC

Chen, H. C., Wu, C. R., Li, K. S. M. & Lee, K-J., 2015 Apr 22, Proceedings of the 2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015. Institute of Electrical and Electronics Engineers Inc., Vol. 2015-April. p. 1281-1284 4 p. 7092589

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Silicon
Networks (circuits)
Granulation
System-on-chip
6 Citations (Scopus)

An efficient 3D-IC on-chip test framework to embed TSV testing in memory BIST

Li, L. C., Hsu, W. H., Lee, K-J. & Hsu, C. L., 2015 Mar 11, 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015. Institute of Electrical and Electronics Engineers Inc., p. 520-525 6 p. 7059059

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Built-in self test
Chip
Data storage equipment
Testing
Integrated circuits
2 Citations (Scopus)

An efficient diagnosis-aware pattern generation procedure for transition faults

Lee, K-J. & Wu, C. H., 2015 Feb 6, Proceedings - 2014 IEEE International Test Conference, ITC 2014. Institute of Electrical and Electronics Engineers Inc., 7035361. (Proceedings - International Test Conference; vol. 2015-February).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Fault
Networks (circuits)
Failure analysis
Program processors
Compaction
4 Citations (Scopus)

Improve transition fault diagnosability via observation point insertion

Wu, C. H., Wang, Y. D. & Lee, K-J., 2015 May 28, 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015. Institute of Electrical and Electronics Engineers Inc., 7114571. (2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Networks (circuits)
2014
7 Citations (Scopus)

An efficient diagnosis method to deal with multiple fault-pairs simultaneously using a single circuit model

Wu, C. H., Lee, K-J. & Lien, W. C., 2014 Jan 1, Proceedings - 2014 IEEE 32nd VLSI Test Symposium, VTS 2014. IEEE Computer Society, 6818790. (Proceedings of the IEEE VLSI Test Symposium).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Networks (circuits)
Data structures
5 Citations (Scopus)

An efficient diagnosis pattern generation procedure to distinguish stuck-at faults and bridging faults

Wu, C. H. & Lee, K-J., 2014 Dec 7, Proceedings - 23rd Asian Test Symposium, ATS 2014. IEEE Computer Society, p. 306-311 6 p. 06979118. (Proceedings of the Asian Test Symposium).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Defects
Networks (circuits)
Failure analysis
Program processors
Integrated circuits
1 Citation (Scopus)

Efficient pattern generation for transition-fault diagnosis using combinational circuit model

Wang, Y. D. & Lee, K-J., 2014 Jan 23, Proceedings - 2014 IEEE 12th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014. Zhou, J. & Tang, T-A. (eds.). Institute of Electrical and Electronics Engineers Inc., 7021499. (Proceedings - 2014 IEEE 12th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Combinatorial circuits
Failure analysis
Networks (circuits)
3 Citations (Scopus)

Output-bit selection with X-avoidance using multiple counters for test-response compaction

Lien, W. C., Lee, K-J., Chakrabarty, K. & Hsieh, T. Y., 2014 Jan 1, Proceedings - 2014 19th IEEE European Test Symposium, ETS 2014. IEEE Computer Society, 6847823. (Proceedings - 2014 19th IEEE European Test Symposium, ETS 2014).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Compaction
Networks (circuits)
Experiments
2 Citations (Scopus)

Output selection for test response compaction based on multiple counters

Lien, W. C., Lee, K-J., Chakrabarty, K. & Hsieh, T. Y., 2014 Jan 1, Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014. IEEE Computer Society, 6834865. (Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Compaction
2013
5 Citations (Scopus)

An efficient deadlock-free multicast routing algorithm for mesh-based networks-on-chip

Lee, K-J., Chang, C. Y. & Yang, H. Y., 2013 Aug 15, 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013. 6533824. (2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Routing algorithms
Routers
Network-on-chip
Communication
2012
12 Citations (Scopus)

A test-per-clock LFSR reseeding algorithm for concurrent reduction on test sequence length and test data volume

Lien, W. C., Lee, K-J. & Hsieh, T. Y., 2012 Dec 1, Proceedings - 2012 IEEE 21st Asian Test Symposium, ATS 2012. p. 278-283 6 p. 6394216. (Proceedings of the Asian Test Symposium).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Seed
Clocks
Built-in self test
1 Citation (Scopus)

Output bit selection for test response compaction based on a single counter

Lee, K-J., Lien, W. C. & Hsieh, T. Y., 2012 Dec 1, ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings. 6467671. (ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Compaction
Hardware
Networks (circuits)
5 Citations (Scopus)

Routing-efficient implementation of an internal-response-based BIST architecture

Lien, W. C., Hsieh, T. Y. & Lee, K-J., 2012 Jul 25, 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers. 6212622. (2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Built-in self test
Networks (circuits)
Hardware
2011
1 Citation (Scopus)

A rotation-based BIST with self-feedback logic to achieve complete fault coverage

Lien, W. C., Hsieh, T. Y., Tsai, C. T. & Lee, K-J., 2011 Jun 28, Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011. p. 252-255 4 p. 5783623. (Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Built-in self test
Shift registers
Feedback
Networks (circuits)
Experiments
2 Citations (Scopus)

A software/hardware co-debug platform for multi-core systems

Lee, K-J., Su, A., Chen, L. F., Jhou, J. W., Kuo, J. & Liu, M., 2011 Dec 1, Proceedings - 2011 IEEE 9th International Conference on ASIC, ASICON 2011. p. 259-262 4 p. 6157171. (Proceedings of International Conference on ASIC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Hardware
Clocks
Multicore programming
Application programs
Field programmable gate arrays (FPGA)

EPIDETOX: An esl platform for integrated circuit design and tool exploration

Lee, K-J., Chang, C. Y. & Chen, I. J., 2011 Nov 22, Embedded Systems Week 2011, ESWEEK 2011 - Proceedings of the 9th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS'11. p. 381-384 4 p. (Embedded Systems Week 2011, ESWEEK 2011 - Proceedings of the 9th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS'11).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Systems analysis
Integrated circuit design
Application programs
Computer hardware
User interfaces
3 Citations (Scopus)

Multi-core software/hardware co-debug platform with ARM CoreSight, on-chip test architecture and AXI/AHB bus monitor

Su, A. P., Kuo, J., Lee, K-J., Huang, I. J., Jian, G. A., Chien, C. A., Guo, J. I. & Chen, C. H., 2011 Jun 28, Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011. p. 129-134 6 p. 5783594. (Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Hardware
Inspection
Program debugging
Hazards and race conditions
Field programmable gate arrays (FPGA)
2010
7 Citations (Scopus)

A complete logic BIST technology with no storage requirement

Lien, W. C. & Lee, K-J., 2010 Dec 1, Proceedings - 2010 19th IEEE Asian Test Symposium, ATS 2010. p. 129-134 6 p. 5692235. (Proceedings of the Asian Test Symposium).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Built-in self test
Networks (circuits)
Digital circuits
Data storage equipment
3 Citations (Scopus)

Design of on-chip bus with OCP interface

Chang, C. Y., Chang, Y. J., Lee, K-J., Yeh, J. C., Lin, S. Y. & Ma, J. L., 2010 Nov 8, Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010. p. 211-214 4 p. 5496727. (Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Communication
Intellectual property core
2009
11 Citations (Scopus)

A low-cost SOC debug platform based on on-chip test architectures

Lee, K-J., Liang, S. Y. & Su, A., 2009 Dec 1, Proceedings - IEEE International SOC Conference, SOCC 2009. p. 161-164 4 p. 5398067. (Proceedings - IEEE International SOC Conference, SOCC 2009).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Silicon
Costs
Hardware
1 Citation (Scopus)

An efficient multi-phase test technique to perfectly prevent over-detection of acceptable faults for optimal yield improvement via error-tolerance

Hsieh, T. Y., Lee, K-J. & Breuer, M. A., 2009 Dec 1, 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09. p. 255-258 4 p. 5158143. (2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Degradation
Networks (circuits)
Testing
Costs
1 Citation (Scopus)

A unified test and debug platform for SOC design

Lee, K-J., Chang, C. Y., Su, A. & Liang, S. Y., 2009 Dec 1, ASICON 2009 - Proceedings, 2009 8th IEEE International Conference on ASIC. p. 577-580 4 p. 5351351. (ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Built-in self test
Testing
Silicon
Failure analysis
Hardware
11 Citations (Scopus)

Full system simulation and verification framework

Lin, J. W., Wang, C. C., Chang, C. Y., Chen, C-H., Lee, K-J., Chu, Y. H., Yeh, J. C. & Hsiao, Y. C., 2009 Dec 1, 5th International Conference on Information Assurance and Security, IAS 2009. p. 165-168 4 p. 5283808. (5th International Conference on Information Assurance and Security, IAS 2009; vol. 1).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Computer hardware
Interfaces (computer)
Particle accelerators
Computer systems
Hardware
23 Citations (Scopus)

Tolerance of performance degrading faults for effective yield improvement

Hsieh, T. Y., Breuer, M. A., Annavaram, M., Gupta, S. K. & Lee, K-J., 2009 Dec 15, International Test Conference, ITC 2009 - Proceedings. 5355594. (Proceedings - International Test Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Tolerance
Fault
Degradation
Clocks
Throughput
2 Citations (Scopus)

Transaction level modeling and design space exploration for SOC test architectures

Chang, C. Y., Hsiao, C. Y., Lee, K-J. & Su, A. P., 2009 Dec 1, Proceedings of the 18th Asian Test Symposium, ATS 2009. p. 200-205 6 p. 5359358. (Proceedings of the Asian Test Symposium).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

System buses
Built-in self test
Testing
Program processors
Data storage equipment
2008
2 Citations (Scopus)

A hybrid self-testing methodology of processor cores

Lu, T. H., Chen, C-H. & Lee, K-J., 2008 Sep 19, 2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008. p. 3378-3381 4 p. 4542183. (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Pipelines
Information use
Testing
System-on-chip
1 Citation (Scopus)

A hybrid software-based self-testing methodology for embedded processor

Lu, T. H., Chen, C-H. & Lee, K-J., 2008 Dec 1, Proceedings of the 23rd Annual ACM Symposium on Applied Computing, SAC'08. p. 1528-1534 7 p. (Proceedings of the ACM Symposium on Applied Computing).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Testing
Pipelines
Networks (circuits)
System-on-chip
14 Citations (Scopus)

A software-based test methodology for direct-mapped data cache

Lin, Y. C., Tsai, Y. Y., Lee, K-J., Yen, C. W. & Chen, C-H., 2008 Dec 1, Proceedings of the 17th Asian Test Symposium, ATS 2008. p. 363-368 6 p. 4711618. (Proceedings of the Asian Test Symposium).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Data storage equipment
Physical addresses
Reduced instruction set computing
Random access storage
Testing

A systematic methodology to employ error-tolerance for yield improvement

Hsieh, T. Y., Lee, K-J., Lu, C. L. & Breuer, M. A., 2008 Sep 5, 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT. p. 105-108 4 p. 4542423. (2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Discrete cosine transforms
Integrated circuits
Networks (circuits)
8 Citations (Scopus)

Programmable System-on-chip (SoC) for silicon prototyping

Huang, C. M., Wu, C. M., Yang, C. C., Lee, K-J. & Wey, C. L., 2008 Dec 29, 2008 IEEE International Symposium on Industrial Electronics, ISIE 2008. p. 1976-1981 6 p. 4677107. (IEEE International Symposium on Industrial Electronics).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Silicon
System-on-chip
Costs
Fabrication
7 Citations (Scopus)

Turbo1500: Toward core-based design for test and diagnosis using the IEEE 1500 standard

Wang, L. T., Apte, R., Wu, S., Sheu, B., Lee, K-J., Wen, X., Jone, W. B., Yeh, C. H., Wang, W. S., Chao, H. J., Guo, J., Liu, J., Niu, Y., Sung, Y. C., Wang, C. C. & Li, F., 2008 Dec 1, Proceedings - International Test Conference 2008, ITC 2008. 4700630. (Proceedings - International Test Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Automation
Chip
Printed circuit boards
Printed Circuit Board
Wrapper