• 1331 Citations
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1990 …2020
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Research Output 1990 2019

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2019

An Efficient Diagnosis-Aware ATPG Procedure to Enhance Diagnosis Resolution and Test Compaction

Wu, C. H., Lee, K-J. & Reddy, S. M., 2019 Sep 1, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 27, 9, p. 2105-2118 14 p., 8742768.

Research output: Contribution to journalArticle

Automatic test pattern generation
Compaction
Networks (circuits)
Trimming
Fault detection
Networks (circuits)
Transistors
1 Citation (Scopus)

On-Chip Self-Test Methodology With All Deterministic Compressed Test Patterns Recorded in Scan Chains

Lee, K-J., Chen, B. R. & Kochte, M. A., 2019 Feb 1, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 38, 2, p. 309-321 13 p., 8299475.

Research output: Contribution to journalArticle

Built-in self test
Failure analysis
Clocks
Controllers
Networks (circuits)
2018
1 Citation (Scopus)

A Hybrid Multicast Routing Approach with Enhanced Methods for Mesh-Based Networks-on-Chip

Wu, C. W., Lee, K-J. & Su, A. P., 2018 Sep 1, In : IEEE Transactions on Computers. 67, 9, p. 1231-1245 15 p., 8309347.

Research output: Contribution to journalArticle

Multicast Routing
Routing algorithms
Deadlock
Routing Algorithm
Mesh

A Repair-for-Diagnosis Methodology for Logic Circuits

Wu, C. H., Lin, S. L., Lee, K-J. & Reddy, S. M., 2018 Nov 1, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 26, 11, p. 2254-2267 14 p., 8423443.

Research output: Contribution to journalArticle

Logic circuits
Repair
Defects
Networks (circuits)
Failure analysis
2017
2 Citations (Scopus)

Built-In Test and Diagnosis for TSVs with Different Placement Topologies and Crosstalk Impact Ranges

Hsu, W. H., Kochte, M. A. & Lee, K-J., 2017 Jun 1, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 36, 6, p. 1004-1017 14 p.

Research output: Contribution to journalArticle

Crosstalk
Topology
Silicon
Testing
9 Citations (Scopus)

Test Stimulus Compression Based on Broadcast Scan with One Single Input

Chen, J. Z. & Lee, K-J., 2017 Jan 1, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 36, 1, p. 184-197 14 p., 7463526.

Research output: Contribution to journalArticle

Networks (circuits)
Switches
Flip flop circuits
Data reduction
2015

A high-performance SoC debug platform

Liu, K. K., Hsu, W. H. & Lee, K-J., 2015 Jan 1, In : Smart Science. 3, 4, p. 202-208 7 p.

Research output: Contribution to journalArticle

High Performance
Debugging
Design Automation
Automation
Trigger
2014
22 Citations (Scopus)

Capture-power-safe test pattern determination for at-speed scan-based testing

Li, Y. H., Lien, W. C., Lin, I-C. & Lee, K-J., 2014 Jan 1, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 33, 1, p. 127-138 12 p., 6685941.

Research output: Contribution to journalArticle

Testing
Refining
Networks (circuits)
4 Citations (Scopus)

Efficient LFSR Reseeding Based on Internal-Response Feedback

Lien, W. C., Lee, K-J., Hsieh, T. Y. & Chakrabarty, K., 2014 Dec 3, In : Journal of Electronic Testing: Theory and Applications (JETTA). 30, 6, p. 673-685 13 p.

Research output: Contribution to journalArticle

Feedback
Seed
Networks (circuits)
Built-in self test
Integrated circuits
3 Citations (Scopus)

On deadlock problem of on-chip buses supporting out-of-order transactions

Chang, C. Y. & Lee, K-J., 2014 Jan 1, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 22, 3, p. 484-496 13 p., 6490417.

Research output: Contribution to journalArticle

Network protocols
Interfaces (computer)
Communication
2013
10 Citations (Scopus)

An efficient on-chip test generation scheme based on programmable and multiple twisted-ring counters

Lien, W. C., Lee, K-J., Hsieh, T. Y. & Ang, W. L., 2013 Aug 5, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 32, 8, p. 1254-1264 11 p., 6559094.

Research output: Contribution to journalArticle

Seed
Networks (circuits)
Inventory control
Data storage equipment
5 Citations (Scopus)

Counter-based output selection for test response compaction

Lien, W. C., Lee, K-J., Hsieh, T. Y., Chakrabarty, K. & Wu, Y. H., 2013 Jan 7, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 32, 1, p. 152-164 13 p., 6387700.

Research output: Contribution to journalArticle

Compaction
Hardware
Networks (circuits)
2012
9 Citations (Scopus)

Efficient overdetection elimination of acceptable faults for yield improvement

Lee, K-J., Hsieh, T. Y. & Breuer, M. A., 2012 May 1, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 31, 5, p. 754-764 11 p., 6186858.

Research output: Contribution to journalArticle

Networks (circuits)
Automatic test pattern generation
Testing
2011
5 Citations (Scopus)

An error-tolerance-based test methodology to support product grading for yield enhancement

Hsieh, T. Y., Lee, K-J. & Breuer, M. A., 2011 Jun 1, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 30, 6, p. 930-934 5 p., 5768131.

Research output: Contribution to journalArticle

Networks (circuits)
27 Citations (Scopus)
Pipelines
Testing
Macros
Data storage equipment
13 Citations (Scopus)

Programmable system-on-chip for silicon prototyping

Huang, C. M., Wu, C. M., Yang, C. C., Chen, S. L., Chen, C. S., Wang, J. J., Lee, K-J. & Wey, C. L., 2011 Mar 1, In : IEEE Transactions on Industrial Electronics. 58, 3, p. 830-838 9 p., 4926187.

Research output: Contribution to journalArticle

Silicon
System-on-chip
Costs
Fabrication
14 Citations (Scopus)

Test response compaction via output bit selection

Lee, K-J., Lien, W. C. & Hsieh, T. Y., 2011 Oct 1, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 30, 10, p. 1534-1544 11 p., 6022010.

Research output: Contribution to journalArticle

Compaction
Networks (circuits)
Automatic test pattern generation
Shift registers
Set theory
2010
11 Citations (Scopus)

On-chip SOC test platform design based on IEEE 1500 standard

Lee, K-J., Hsieh, T. Y., Chang, C. Y., Hong, Y. T. & Huang, W. C., 2010 Jul 1, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 18, 7, p. 1134-1139 6 p., 5229351.

Research output: Contribution to journalArticle

Built-in self test
Data storage equipment
Testing
Embedded systems
Field programmable gate arrays (FPGA)
2008
17 Citations (Scopus)

An error rate based test methodology to support error-tolerance

Hsieh, T. Y., Lee, K-J. & Breuer, M. A., 2008 Mar 1, In : IEEE Transactions on Reliability. 57, 1, p. 204-214 11 p.

Research output: Contribution to journalArticle

Sampling
Networks (circuits)
2007

A design automation system for SOC test platform

Huang, W. C., Lee, K-J., Chang, C. Y. & Wu, Y. H., 2007 Jun 1, In : International Journal of Electrical Engineering. 14, 3, p. 219-227 9 p.

Research output: Contribution to journalArticle

Automation
User interfaces
Controllers
Testing
1 Citation (Scopus)

Preventing over-detection of acceptable faults for yield enhancement

Hsieh, T. Y., Lee, K-J. & Breuer, M. A., 2007 Jun, In : International Journal of Electrical Engineering. 14, 3, p. 185-193 9 p.

Research output: Contribution to journalArticle

Degradation
Defects
Testing
2004
49 Citations (Scopus)

Test power reduction with multiple capture orders

Lee, K-J., Hsu, S. J. & Ho, C. M., 2004, In : Proceedings of the Asian Test Symposium. p. 26-31 6 p.

Research output: Contribution to journalArticle

Energy dissipation
Networks (circuits)
Testing
2003
Clocks
Demultiplexing
Broadcasting
Compression testing
Shift registers
23 Citations (Scopus)

Test pattern generation and clock disabling for simultaneous test time and power reduction

Chen, J. J., Yang, C. K. & Lee, K-J., 2003 Mar 1, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 22, 3, p. 363-369 7 p.

Research output: Contribution to journalArticle

Clocks
Energy dissipation
Networks (circuits)
Electric power utilization
Testing
2002
3 Citations (Scopus)

A 0.5 μm concurrent testable chip of a fifth-order gm-C filter

Lee, K-J. & Wang, W. C., 2002 Sep 1, In : Analog Integrated Circuits and Signal Processing. 32, 3, p. 231-247 17 p.

Research output: Contribution to journalArticle

Networks (circuits)
Error detection
Low pass filters
Testing
Electric potential
5 Citations (Scopus)

A current-mode BIST structure of DACs

Wen, Y. C. & Lee, K-J., 2002 Apr 1, In : Measurement: Journal of the International Measurement Confederation. 31, 3, p. 147-163 17 p.

Research output: Contribution to journalArticle

Built-in Self-test
self tests
Built-in self test
Voltage
Nonlinearity
9 Citations (Scopus)

An efficient BIST method for distributed small buffers

Jone, W. B., Huang, D. C., Wu, S. C. & Lee, K-J., 2002 Aug 1, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 10, 4, p. 512-514 3 p.

Research output: Contribution to journalArticle

Data storage equipment
Testing
Hardware

An efficient deterministic test pattern generator for scan-based BIST environment

Wang, W. L. & Lee, K-J., 2002 Feb 1, In : Journal of Electronic Testing: Theory and Applications (JETTA). 18, 1, p. 43-53 11 p.

Research output: Contribution to journalArticle

Built-in self test
Shift registers
Feedback
Logic circuits
Clocks
2 Citations (Scopus)
Networks (circuits)
Testing
2001
Integrated circuit design
Intellectual property core
5 Citations (Scopus)

A low-power LFSR architecture

Huang, T. C. & Lee, K-J., 2001 Jan 1, In : Proceedings of the Asian Test Symposium. 1 p., 80.

Research output: Contribution to journalArticle

Built-in self test
Clocks
Networks (circuits)
Analog circuits
Switches
16 Citations (Scopus)

An on-chip march pattern generator for testing embedded memory cores

Wang, W. L., Lee, K-J. & Wang, J. F., 2001 Oct 1, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 9, 5, p. 730-735 6 p.

Research output: Contribution to journalArticle

Data storage equipment
Testing
Shift registers
Hardware
Shift registers
Feedback
Built-in self test
Clocks
Costs
42 Citations (Scopus)
Electric power utilization
Networks (circuits)
Experiments
6 Citations (Scopus)

Token scan cell for low power testing

Huang, T. C. & Lee, K-J., 2001 May 24, In : Electronics Letters. 37, 11, p. 678-679 2 p.

Research output: Contribution to journalArticle

Flip flop circuits
Networks (circuits)
Testing
Clocks
Scanning
2000
2 Citations (Scopus)

Accelerated test pattern generators for mixed-mode BIST environments

Wang, W. L. & Lee, K-J., 2000, In : Proceedings of the Asian Test Symposium. p. 368-373 6 p.

Research output: Contribution to journalArticle

Built-in self test
Shift registers
Feedback
Clocks
Costs
38 Citations (Scopus)

An on chip ADC test structure

Wen, Y. C. & Lee, K-J., 2000, In : Proceedings -Design, Automation and Test in Europe, DATE. p. 221-225 5 p., 840042.

Research output: Contribution to journalArticle

Digital to analog conversion
Built-in self test
Specifications
Testing
11 Citations (Scopus)

Hierarchical test control architecture for core based design

Lee, K-J. & Huang, C. I., 2000, In : Proceedings of the Asian Test Symposium. p. 248-253 6 p.

Research output: Contribution to journalArticle

Testing
Integrated circuit design
System-on-chip
Intellectual property core
7 Citations (Scopus)

Reducing test application time by scan flip-flops sharing

Chang, S. C., Lee, K-J., Wu, Z. Z. & Jone, W. B., 2000 Jan 1, In : IEE Proceedings: Computers and Digital Techniques. 147, 1, p. 42-48 7 p.

Research output: Contribution to journalArticle

Flip flop circuits
Flip
Sharing
Networks (circuits)
Fault
1999
26 Citations (Scopus)

A current-mode testable design of operational transconductance amplifier-capacitor filters

Lee, K-J., Wang, W. C. & Huang, K. S., 1999 Dec 1, In : IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing. 46, 4, p. 401-413 13 p.

Research output: Contribution to journalArticle

Operational amplifiers
Capacitors
Error detection
Networks (circuits)
High definition television
1 Citation (Scopus)

BIFEST: A built-in intermediate fault effect sensing and test generation system for cmos bridging faults

Lee, K-J., Tang, J. J. & Huang, T. C., 1999 Jan 1, In : ACM Transactions on Design Automation of Electronic Systems. 4, 2, p. 194-218 25 p.

Research output: Contribution to journalArticle

Electric potential
Networks (circuits)
Monitoring
Sensors
Testing
49 Citations (Scopus)

Broadcasting test patterns to multiple circuits

Lee, K-J., Chen, J. J. & Huang, C. H., 1999 Dec 1, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 18, 12, p. 1793-1802 10 p.

Research output: Contribution to journalArticle

Broadcasting
Sequential circuits
Networks (circuits)
Compaction
Automatic test pattern generation
2 Citations (Scopus)

Embedded march algorithm test pattern generator for memory testing

Wang, W. L., Lee, K-J. & Wang, J. F., 1999, In : International Symposium on VLSI Technology, Systems, and Applications, Proceedings. p. 211-214 4 p.

Research output: Contribution to journalArticle

test pattern generators
systems-on-a-chip
Data storage equipment
Testing
hardware
1998
10 Citations (Scopus)

A built-in current sensor based on current-mode design

Lee, K-J. & Tang, J. J., 1998 Dec 1, In : IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing. 45, 1, p. 133-137 5 p.

Research output: Contribution to journalArticle

Sensors
Testing
Temperature

A general structure of feedback shift registers for built-in self test

Lee, K-J., Wang, W. L. & Wang, J. F. A., 1998 Sep, In : Journal of Information Science and Engineering. 14, 3, p. 645-667 23 p.

Research output: Contribution to journalArticle

Built-in self test
Shift registers
Feedback
Flip flop circuits
Polynomials

A graph representation for programmable logic arrays to facilitate testing and logic design

Tang, J. J., Lee, K-J. & Liu, B-D., 1998 Dec 1, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 17, 10, p. 1030-1043 14 p.

Research output: Contribution to journalArticle

Logic design
Testing
Automatic test pattern generation
Directed graphs
Data structures
20 Citations (Scopus)

BIST structure for DAC testing

Wen, Y. C. & Lee, K-J., 1998 Jun 11, In : Electronics Letters. 34, 12, p. 1173-1174 2 p.

Research output: Contribution to journalArticle

Built-in self test
Digital to analog conversion
Testing
Electric potential
1 Citation (Scopus)

Concurrent error detection, diagnosis, and fault tolerance for switched-capacitor filters

Lee, K-J. & Kuo, C. H., 1998 Dec, In : Journal of Information Science and Engineering. 14, 4, p. 863-890 28 p.

Research output: Contribution to journalArticle

Switched capacitor filters
Error detection
Fault tolerance
tolerance
Networks (circuits)