• 1350 Citations
  • 19 h-Index
1990 …2020

Research output per year

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Research Output

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Conference article
2013

A new LFSR reseeding scheme via internal response feedback

Lien, W. C., Lee, K-J., Hsieh, T. Y. & Chakrabarty, K., 2013 Jan 1, In : Proceedings of the Asian Test Symposium. p. 97-102 6 p., 6690622.

Research output: Contribution to journalConference article

3 Citations (Scopus)
2005

A complete memory address generator for scan based march algorithms

Wang, W. L. & Lee, K-J., 2005 Dec 9, In : Records of the IEEE International Workshop on Memory Technology, Design and Testing. p. 83-88 6 p.

Research output: Contribution to journalConference article

10 Citations (Scopus)

An embedded processor based SOC test platform

Lee, K-J., Chu, C. Y. & Hong, Y. T., 2005 Dec 1, In : Proceedings - IEEE International Symposium on Circuits and Systems. p. 2983-2986 4 p., 1465254.

Research output: Contribution to journalConference article

25 Citations (Scopus)
2004

A low-cost diagnosis methodology for pipelined A/D converters

Huang, C. H., Lee, K. J. & Chang, S. J., 2004 Dec 1, In : Proceedings of the Asian Test Symposium. p. 296-301 6 p.

Research output: Contribution to journalConference article

5 Citations (Scopus)
2001

A token scan architecture for low power testing

Huang, T. C. & Lee, K-J., 2001 Dec 1, In : IEEE International Test Conference (TC). p. 660-669 10 p.

Research output: Contribution to journalConference article

31 Citations (Scopus)
2000

Accelerated test pattern generators for mixed-mode BIST environments

Wang, W. L. & Lee, K. J., 2000 Dec 1, In : Proceedings of the Asian Test Symposium. p. 368-373 6 p.

Research output: Contribution to journalConference article

2 Citations (Scopus)

An on chip ADC test structure

Wen, Y. C. & Lee, K. J., 2000 Dec 1, In : Proceedings -Design, Automation and Test in Europe, DATE. p. 221-225 5 p., 840042.

Research output: Contribution to journalConference article

38 Citations (Scopus)

Hierarchical test control architecture for core based design

Lee, K. J. & Huang, C. I., 2000 Dec 1, In : Proceedings of the Asian Test Symposium. p. 248-253 6 p.

Research output: Contribution to journalConference article

11 Citations (Scopus)

Peak-power reduction for multiple-scan circuits during test application

Lee, K. J., Huang, T. C. & Chen, J. J., 2000 Dec 1, In : Proceedings of the Asian Test Symposium. p. 453-458 6 p.

Research output: Contribution to journalConference article

60 Citations (Scopus)
1999

Input control technique for power reduction in scan circuits during test application

Huang, T. C. & Lee, K. J., 1999 Dec 1, In : Proceedings of the Asian Test Symposium. p. 315-320 6 p.

Research output: Contribution to journalConference article

32 Citations (Scopus)
1998

On the determination of threshold voltages for CMOS gates to facilitate test pattern generation and fault simulation

Lee, K. J., Tang, J. J. & Duh, W. Y., 1998 Dec 1, In : Proceedings of the Asian Test Symposium. p. 113-118 6 p.

Research output: Contribution to journalConference article

2 Citations (Scopus)

Using a single input to support multiple scan chains

Lee, K. J., Chen, J. J. & Huang, C. H., 1998 Dec 1, In : IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers. p. 74-78 5 p.

Research output: Contribution to journalConference article

156 Citations (Scopus)
1997

Built-in current sensor designs based on the bulk-driven technique

Huang, T. C., Huang, M. C. & Lee, K. J., 1997 Dec 1, In : Proceedings of the Asian Test Symposium. p. 384-388 5 p.

Research output: Contribution to journalConference article

6 Citations (Scopus)
1996

Combination of automatic test pattern generation and built-in intermediate voltage sensing for detecting CMOS bridging faults

Lee, K-J., Tang, J. J., Huang, T. C. & Tsai, C. L., 1996 Dec 1, In : Proceedings of the Asian Test Symposium. p. 100-105 6 p.

Research output: Contribution to journalConference article

2 Citations (Scopus)

Two modeling techniques for CMOS circuits to enhance test generation and fault simulation for bridging faults

Lee, K-J. & Tang, J. J., 1996 Dec 1, In : Proceedings of the Asian Test Symposium. p. 165-170 6 p.

Research output: Contribution to journalConference article

6 Citations (Scopus)
1995

IDDQ fault model to facilitate the design of built-in current sensor (BICSs)

Tang, J. J., Liu, B. D. & Lee, K. J., 1995 Jan 1, In : Proceedings - IEEE International Symposium on Circuits and Systems. 1, p. 393-396 4 p.

Research output: Contribution to journalConference article

New architecture for analog boundary scan

Lee, K-J., Jeng, S. Y. & Lee, T. P., 1995 Jan 1, In : Proceedings - IEEE International Symposium on Circuits and Systems. 1, p. 409-412 4 p.

Research output: Contribution to journalConference article

2 Citations (Scopus)
1990

A universal test sequence for CMOS scan registers

Lee, K. J. & Breuer, M. A., 1990 Dec 1, In : Proceedings of the Custom Integrated Circuits Conference.

Research output: Contribution to journalConference article

19 Citations (Scopus)
8 Citations (Scopus)