If you made any changes in Pure these will be visible here soon.

Personal profile

Education

  • 2013 PhD, Electrical Engineering, KULeuven, Belgium

Research Interests

  • Semiconductor Physics and Devices

Experience

  • 2009~2013 PhD researcher, Inter-university Microelectronic Centre (imec), Belgium
  • 2014~present Assistant Professor, Department of Electrical Engineering, National Cheng Kung University, Taiwan

Fingerprint Dive into the research topics where Kuo-Hsing Kao is active. These topic labels come from the works of this person. Together they form a unique fingerprint.

  • 15 Similar Profiles
Field effect transistors Engineering & Materials Science
Tunnels Engineering & Materials Science
Gate dielectrics Engineering & Materials Science
Polysilicon Engineering & Materials Science
Thin film transistors Engineering & Materials Science
field effect transistors Physics & Astronomy
Doping (additives) Engineering & Materials Science
Semiconductor materials Engineering & Materials Science

Network Recent external collaboration on country level. Dive into details by clicking on the dots.

Projects 2014 2020

Research Output 2006 2019

Demonstration of annealing-free metal-insulator-semiconductor (mis) ohmic contacts on a gan substrate using low work-function metal ytterbium (yb) and al2o3 interfacial layer

Wu, T. L., Tseng, Y. Y., Huang, C. F., Chen, Z. S., Lin, C. C., Chung, C. J., Huang, P. K. & Kao, K-H., 2019 May 1, WiPDA Asia 2019 - IEEE Workshop on Wide Bandgap Power Devices and Applications in Asia. Institute of Electrical and Electronics Engineers Inc., 8760323. (WiPDA Asia 2019 - IEEE Workshop on Wide Bandgap Power Devices and Applications in Asia).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Ytterbium
Ohmic contacts
Demonstrations
Metals
Annealing

Impact of Semiconductor Permittivity Reduction on Electrical Characteristics of Nanoscale MOSFETs

Chen, S. H., Lian, S. W., Wu, T. R., Chang, T-R., Liou, J. M., Lu, D., Kao, K-H., Chen, N. Y., Lee, W. J. & Tsai, J. H., 2019 Jun 1, In : IEEE Transactions on Electron Devices. 66, 6, p. 2509-2512 4 p., 8704283.

Research output: Contribution to journalArticle

Permittivity
Semiconductor materials
Poisson equation
Threshold voltage
Screening

Voltage Transfer Characteristic Matching by Different Nanosheet Layer Numbers of Vertically Stacked Junctionless CMOS Inverter for SoP/3D-ICs applications

Sung, P. J., Chang, C. Y., Chen, L. Y., Kao, K-H., Su, C. J., Liao, T. H., Fang, C. C., Wang, C. J., Hong, T. C., Jao, C. Y., Hsu, H. S., Luo, S. X., Wang, Y. S., Huang, H. F., Li, J. H., Huang, Y. C., Hsueh, F. K., Wu, C. T., Huang, Y. M., Hou, F. J. & 16 others, Luo, G. L., Huang, Y. C., Shen, Y. L., Ma, W. C. Y., Huang, K. P., Lin, K. L., Samukawa, S., Li, Y., Huang, G. W., Lee, Y. J., Li, J. Y., Wu, W. F., Shieh, J. M., Chao, T. S., Yeh, W. K. & Wang, Y-H., 2019 Jan 16, 2018 IEEE International Electron Devices Meeting, IEDM 2018. Institute of Electrical and Electronics Engineers Inc., p. 21.4.1-21.4.4 8614553. (Technical Digest - International Electron Devices Meeting, IEDM; vol. 2018-December).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Nanosheets
inverters
CMOS
Electric potential
electric potential
1 Citation (Scopus)

A comprehensive study of polymorphic phase distribution of ferroelectric-dielectrics and interfacial layer effects on negative capacitance FETs for Sub-5 nm node

Tang, Y. T., Su, C. J., Wang, Y. S., Kao, K-H., Wu, T. L., Sung, P. J., Hou, F. J., Wang, C. J., Yeh, M. S., Lee, Y. J., Wu, W. F., Huang, G. W., Shieh, J. M., Yeh, W. K. & Wang, Y-H., 2018 Oct 25, 2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018. Institute of Electrical and Electronics Engineers Inc., p. 45-46 2 p. 8510696. (Digest of Technical Papers - Symposium on VLSI Technology; vol. 2018-June).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Field effect transistors
Ferroelectric materials
Capacitance
Depolarization
Tensors
1 Citation (Scopus)

An FET with a Source Tunneling Barrier Showing Suppressed Short-Channel Effects for Low-Power Applications

Hsieh, Y. F., Chen, S. H., Chen, N. Y., Lee, W. J., Tsai, J. H., Chen, C. N., Chiang, M-H., Lu, D. & Kao, K-H., 2018 Mar 1, In : IEEE Transactions on Electron Devices. 65, 3, p. 855-859 5 p.

Research output: Contribution to journalArticle

Field effect transistors
Threshold voltage

Thesis

Fabrication and characterization of IGZO thin film transistors

Author: 俊成, 林., 2016 Aug 23

Supervisor: Kao, K. (Supervisor)

Student thesis: Master's Thesis

Fermi-Level Pinning Effect Analysis and Simulation of Dopingless FETs with Metal-Insulator-Semiconductor Contacts

Author: 亮瑜, 陳., 2018 Jun 26

Supervisor: Kao, K. (Supervisor)

Student thesis: Master's Thesis

Gate Oxide scaling Effect on MOSFETs and TFETs by TCAD Simulations

Author: 磊安, 尤., 2018 Aug 15

Supervisor: Kao, K. (Supervisor)

Student thesis: Master's Thesis

Investigation on Surface Cleaning Interfacial Layer Formation and Ferroelectric Properties on Germanium Substrates

Author: 昱舜, 王., 2018 Sep 6

Supervisor: Kao, K. (Supervisor)

Student thesis: Master's Thesis