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Research Output

2020

Impact of the polarization on time-dependent dielectric breakdown in ferroelectric Hf0.5Zr0.5O2 on Ge substrates

Yang, T. H., Su, C. J., Wang, Y. S., Kao, K. H., Lee, Y. J. & Wu, T. L., 2020 Apr 1, In : Japanese Journal of Applied Physics. 59, SG, SGGB08.

Research output: Contribution to journalArticle

2019

A Comprehensive Kinetical Modeling of Polymorphic Phase Distribution of Ferroelectric-Dielectrics and Interfacial Energy Effects on Negative Capacitance FETs

Tang, Y. T., Fan, C. L., Kao, Y. C., Modolo, N., Su, C. J., Wu, T. L., Kao, K. H., Wu, P. J., Hsaio, S. W., Useinov, A., Su, P., Wu, W. F., Huang, G. W., Shieh, J. M., Yeh, W. K. & Wang, Y. H., 2019 Jun, 2019 Symposium on VLSI Technology, VLSI Technology 2019 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., p. T222-T223 8776508. (Digest of Technical Papers - Symposium on VLSI Technology; vol. 2019-June).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Demonstration of annealing-free metal-insulator-semiconductor (mis) ohmic contacts on a gan substrate using low work-function metal ytterbium (yb) and al2o3 interfacial layer

Wu, T. L., Tseng, Y. Y., Huang, C. F., Chen, Z. S., Lin, C. C., Chung, C. J., Huang, P. K. & Kao, K. H., 2019 May, WiPDA Asia 2019 - IEEE Workshop on Wide Bandgap Power Devices and Applications in Asia. Institute of Electrical and Electronics Engineers Inc., 8760323. (WiPDA Asia 2019 - IEEE Workshop on Wide Bandgap Power Devices and Applications in Asia).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Fabrication of omega-gated negative capacitance finfets and SRAM

Sung, P. J., Su, C. J., Lu, D. D., Luo, S. X., Kao, K. H., Ciou, J. Y., Jao, C. Y., Hsu, H. S., Wang, C. J., Hong, T. C., Liao, T. H., Fang, C. C., Wang, Y. S., Huang, H. F., Li, J. H., Huang, Y. C., Hsueh, F. K., Wu, C. T., Ma, W. C. Y., Huang, K. P. & 6 others, Lee, Y. J., Chao, T. S., Li, J. Y., Wu, W. F., Yeh, W. K. & Wang, Y. H., 2019 Apr, 2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019. Institute of Electrical and Electronics Engineers Inc., 8804663. (2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

First Demonstration of CMOS Inverter and 6T-SRAM Based on GAA CFETs Structure for 3D-IC Applications

Chang, S. W., Li, J. H., Huang, M. K., Huang, Y. C., Huang, S. T., Wang, H. C., Huang, Y. J., Wang, J. Y., Yu, L. W., Huang, Y. F., Hsueh, F. K., Sung, P. J., Wu, C. T., Ma, W. C. Y., Kao, K. H., Lee, Y. J., Lin, C. L., Chuang, R. W., Huang, K. P., Samukawa, S. & 16 others, Li, Y., Lee, W. H., Chu, T. Y., Chao, T. S., Huang, G. W., Wu, W. F., Li, J. Y., Shieh, J. M., Yeh, W. K., Wang, Y. H., Lu, D. D., Wang, C. J., Lin, N. C., Su, C. J., Lo, S. H. & Huang, H. F., 2019 Dec, 2019 IEEE International Electron Devices Meeting, IEDM 2019. Institute of Electrical and Electronics Engineers Inc., 8993525. (Technical Digest - International Electron Devices Meeting, IEDM; vol. 2019-December).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Impact of Semiconductor Permittivity Reduction on Electrical Characteristics of Nanoscale MOSFETs

Chen, S. H., Lian, S. W., Wu, T. R., Chang, T. R., Liou, J. M., Lu, D. D., Kao, K. H., Chen, N. Y., Lee, W. J. & Tsai, J. H., 2019 Jun, In : IEEE Transactions on Electron Devices. 66, 6, p. 2509-2512 4 p., 8704283.

Research output: Contribution to journalArticle

2 Citations (Scopus)

Voltage Transfer Characteristic Matching by Different Nanosheet Layer Numbers of Vertically Stacked Junctionless CMOS Inverter for SoP/3D-ICs applications

Sung, P. J., Chang, C. Y., Chen, L. Y., Kao, K. H., Su, C. J., Liao, T. H., Fang, C. C., Wang, C. J., Hong, T. C., Jao, C. Y., Hsu, H. S., Luo, S. X., Wang, Y. S., Huang, H. F., Li, J. H., Huang, Y. C., Hsueh, F. K., Wu, C. T., Huang, Y. M., Hou, F. J. & 16 others, Luo, G. L., Huang, Y. C., Shen, Y. L., Ma, W. C. Y., Huang, K. P., Lin, K. L., Samukawa, S., Li, Y., Huang, G. W., Lee, Y. J., Li, J. Y., Wu, W. F., Shieh, J. M., Chao, T. S., Yeh, W. K. & Wang, Y. H., 2019 Jan 16, 2018 IEEE International Electron Devices Meeting, IEDM 2018. Institute of Electrical and Electronics Engineers Inc., p. 21.4.1-21.4.4 8614553. (Technical Digest - International Electron Devices Meeting, IEDM; vol. 2018-December).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)
2018

A comprehensive study of polymorphic phase distribution of ferroelectric-dielectrics and interfacial layer effects on negative capacitance FETs for Sub-5 nm node

Tang, Y. T., Su, C. J., Wang, Y. S., Kao, K. H., Wu, T. L., Sung, P. J., Hou, F. J., Wang, C. J., Yeh, M. S., Lee, Y. J., Wu, W. F., Huang, G. W., Shieh, J. M., Yeh, W. K. & Wang, Y. H., 2018 Oct 25, 2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018. Institute of Electrical and Electronics Engineers Inc., p. 45-46 2 p. 8510696. (Digest of Technical Papers - Symposium on VLSI Technology; vol. 2018-June).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

An FET with a Source Tunneling Barrier Showing Suppressed Short-Channel Effects for Low-Power Applications

Hsieh, Y. F., Chen, S. H., Chen, N. Y., Lee, W. J., Tsai, J. H., Chen, C. N., Chiang, M-H., Lu, D. & Kao, K-H., 2018 Mar 1, In : IEEE Transactions on Electron Devices. 65, 3, p. 855-859 5 p.

Research output: Contribution to journalArticle

1 Citation (Scopus)

Ge nanowire FETs with HfZrOx ferroelectric gate stack exhibiting SS of sub-60 mV/dec and biasing effects on ferroelectric reliability

Su, C. J., Hong, T. C., Tsou, Y. C., Hou, F. J., Sung, P. J., Yeh, M. S., Wan, C. C., Kao, K. H., Tang, Y. T., Chiu, C. H., Wang, C. J., Chung, S. T., You, T. Y., Huang, Y. C., Wu, C. T., Lin, K. L., Luo, G. L., Huang, K. P., Lee, Y. J., Chao, T. S. & 5 others, Wu, W. F., Huang, G. W., Shieh, J. M., Yeh, W. K. & Wang, Y. H., 2018 Jan 23, 2017 IEEE International Electron Devices Meeting, IEDM 2017. Institute of Electrical and Electronics Engineers Inc., p. 15.4.1-15.4.4 (Technical Digest - International Electron Devices Meeting, IEDM).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Citations (Scopus)

Junctionless FETs with a Fin Body for Multi-VTH and Dynamic Threshold Operation

Kumar, M. P. V., Lin, J. Y., Kao, K. H. & Chao, T. S., 2018 Aug, In : IEEE Transactions on Electron Devices. 65, 8, p. 3535-3542 8 p., 8399532.

Research output: Contribution to journalArticle

4 Citations (Scopus)

Significance of Multivalley and Nonparabolic Band Structure for GeSn TFET Simulation

Kumar, K., Hsieh, Y. F., Liao, J. H., Kao, K. H. & Wang, Y. H., 2018 Oct, In : IEEE Transactions on Electron Devices. 65, 10, p. 4709-4715 7 p., 8445683.

Research output: Contribution to journalArticle

2 Citations (Scopus)
2017

A dopingless FET with metal-insulator-semiconductor contacts

Kao, K. H. & Chen, L. Y., 2017 Jan, In : IEEE Electron Device Letters. 38, 1, p. 5-8 4 p., 7742896.

Research output: Contribution to journalArticle

11 Citations (Scopus)

High performance complementary Ge peaking FinFETs by room temperature neutral beam oxidation for sub-7 nm technology node applications

Lee, Y. J., Hong, T. C., Hsueh, F. K., Sung, P. J., Chen, C. Y., Chuang, S. S., Cho, T. C., Noda, S., Tsou, Y. C., Kao, K. H., Wu, C. T., Yu, T. Y., Jian, Y. L., Su, C. J., Huang, Y. M., Huang, W. H., Chen, B. Y., Chen, M. C., Huang, K. P., Li, J. Y. & 10 others, Chen, M. J., Li, Y., Samukawa, S., Wu, W. F., Huang, G. W., Shieh, J. M., Tseng, T. Y., Chao, T. S., Wang, Y. H. & Yeh, W. K., 2017 Jan 31, 2016 IEEE International Electron Devices Meeting, IEDM 2016. Institute of Electrical and Electronics Engineers Inc., p. 33.5.1-33.5.4 7838535. (Technical Digest - International Electron Devices Meeting, IEDM).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Improving the Electrical Performance of a Quantum Well FET with a Shell Doping Profile by Heterojunction Optimization

Kumar, M. P. V., Hu, C. Y., Walke, A. M., Kao, K. H. & Chao, T. S., 2017 Sep, In : IEEE Transactions on Electron Devices. 64, 9, p. 3563-3568 6 p., 7990547.

Research output: Contribution to journalArticle

3 Citations (Scopus)

Nano-scaled Ge FinFETs with low temperature ferroelectric HfZrO x on specific interfacial layers exhibiting 65% S.S. reduction and improved I ON

Su, C. J., Tang, Y. T., Tsou, Y. C., Sung, P. J., Hou, F. J., Wang, C. J., Chung, S. T., Hsieh, C. Y., Yeh, Y. S., Hsueh, F. K., Kao, K-H., Chuang, S. S., Wu, C. T., You, T. Y., Jian, Y. L., Chou, T. H., Shen, Y. L., Chen, B. Y., Luo, G. L., Hong, T. C. & 10 others, Huang, K. P., Chen, M. C., Lee, Y. J., Chao, T. S., Tseng, T. Y., Wu, W. F., Huang, G. W., Shieh, J. M., Yeh, W. K. & Wang, Y-H., 2017 Jul 31, 2017 Symposium on VLSI Technology, VLSI Technology 2017. Institute of Electrical and Electronics Engineers Inc., p. T152-T153 7998159. (Digest of Technical Papers - Symposium on VLSI Technology).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

16 Citations (Scopus)

Ultra-shallow junction formation by monolayer doping process in single crystalline Si and Ge for future CMOS devices

Chuang, S. S., Cho, T. C., Sung, P. J., Kao, K. H., Chen, H. J. H., Lee, Y. J., Current, M. I. & Tseng, T. Y., 2017 Jan 1, In : ECS Journal of Solid State Science and Technology. 6, 5, p. P350-P355

Research output: Contribution to journalArticle

6 Citations (Scopus)

Undoped and doped junctionless FETs: Source/drain contacts and immunity to random dopant fluctuation

Chen, L. Y., Hsieh, Y. F. & Kao, K-H., 2017 Jun 1, In : IEEE Electron Device Letters. 38, 6, p. 708-711 4 p., 7891976.

Research output: Contribution to journalArticle

4 Citations (Scopus)

Undoped SiGe FETs with metal-insulator-semiconductor contacts

Chen, L. Y., Hsieh, Y. F. & Kao, K. H., 2017 Dec 29, 2017 Silicon Nanoelectronics Workshop, SNW 2017. Institute of Electrical and Electronics Engineers Inc., p. 95-96 2 p. 8242314. (2017 Silicon Nanoelectronics Workshop, SNW 2017; vol. 2017-January).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2016

ELECTROMECHANICAL DEVICE WITH LIGHT GATING AND OPERATIONAL METHODS THEREOF

Kao, K-H., 2016 May 16, Patent No. I552343

Research output: Patent

2015

A novel junctionless FinFET structure with sub-5nm shell doping profile by molecular monolayer doping and microwave annealing

Lee, Y. J., Cho, T. C., Kao, K-H., Sung, P. J., Hsueh, F. K., Huang, P. C., Wu, C. T., Hsu, S. H., Huang, W. H., Chen, H. C., Li, Y., Current, M. I., Hengstebeck, B., Marino, J., Büyüklimanli, T., Shieh, J. M., Chao, T. S., Wu, W. F. & Yeh, W. K., 2015 Feb 20, In : Technical Digest - International Electron Devices Meeting, IEDM. 2015-February, February, p. 32.7.1-32.7.4 7047158.

Research output: Contribution to journalConference article

19 Citations (Scopus)

Diamond-shaped Ge and Ge0.9Si0.1 gate-all-around nanowire FETs with four {111} facets by dry etch technology

Lee, Y. J., Hou, F. J., Chuang, S. S., Hsueh, F. K., Kao, K. H., Sung, P. J., Yuan, W. Y., Yao, J. Y., Lu, Y. C., Lin, K. L., Wu, C. T., Chen, H. C., Chen, B. Y., Huang, G. W., Chen, H. J. H., Li, J. Y., Li, Y., Samukawa, S., Chao, T. S., Tseng, T. Y. & 3 others, Wu, W. F., Hou, T. H. & Yeh, W. K., 2015 Feb 16, 2015 IEEE International Electron Devices Meeting, IEDM 2015. Institute of Electrical and Electronics Engineers Inc., p. 15.1.1-15.1.4 7409701. (Technical Digest - International Electron Devices Meeting, IEDM; vol. 2016-February).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

High performance poly Si junctionless transistors with sub-5nm conformally doped layers by molecular monolayer doping and microwave incorporating CO2 laser annealing for 3D stacked ICs applications

Lee, Y. J., Cho, T. C., Sung, P. J., Kao, K. H., Hsueh, F. K., Hou, F. J., Chen, P. C., Chen, H. C., Wu, C. T., Hsu, S. H., Chen, Y. J., Huang, Y. M., Hou, Y. F., Huang, W. H., Yang, C. C., Chen, B. Y., Lin, K. L., Chen, M. C., Shen, C. H., Huang, G. W. & 8 others, Huang, K. P., Current, M. I., Li, Y., Samukawa, S., Wu, W. F., Shieh, J. M., Chao, T. S. & Yeh, W. K., 2015 Feb 16, 2015 IEEE International Electron Devices Meeting, IEDM 2015. Institute of Electrical and Electronics Engineers Inc., p. 6.2.1-6.2.4 7409638. (Technical Digest - International Electron Devices Meeting, IEDM; vol. 2016-February).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

14 Citations (Scopus)

Impacts of the Shell Doping Profile on the Electrical Characteristics of Junctionless FETs

Kumar, M. P. V., Hu, C. Y., Kao, K-H., Lee, Y. J. & Chao, T. S., 2015 Sep 7, In : IEEE Transactions on Electron Devices. 62, 11, p. 3541-3546 6 p., 7244201.

Research output: Contribution to journalArticle

20 Citations (Scopus)

Perspective of tunnel-FET for future low-power technology nodes

Verhulst, A. S., Verreck, D., Smets, Q., Kao, K. H., Van De Put, M., Rooyackers, R., Sorée, B., Vandooren, A., De Meyer, K., Groeseneken, G., Heyns, M. M., Mocuta, A., Collaert, N. & Thean, A. V. Y., 2015 Feb 20, 2014 IEEE International Electron Devices Meeting, IEDM 2014. February ed. Institute of Electrical and Electronics Engineers Inc., p. 30.2.1-30.2.4 7047140. (Technical Digest - International Electron Devices Meeting, IEDM; vol. 2015-February, no. February).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Citations (Scopus)
2014

Compressively strained SiGe band-to-band tunneling model calibration based on p-i-n diodes and prospect of strained SiGe tunneling field-effect transistors

Kao, K-H., Verhulst, A. S., Rooyackers, R., Douhard, B., Delmotte, J., Bender, H., Richard, O., Vandervorst, W., Simoen, E., Hikavyy, A., Loo, R., Arstila, K., Collaert, N., Thean, A., Heyns, M. M. & Meyer, K. D., 2014 Dec 7, In : Journal of Applied Physics. 116, 21, 214506.

Research output: Contribution to journalArticle

16 Citations (Scopus)

Fabrication and analysis of a Si/Si0.55Ge0.45 heterojunction line tunnel FET

Walke, A. M., Vandooren, A., Rooyackers, R., Leonelli, D., Hikavyy, A., Loo, R., Verhulst, A. S., Kao, K. H., Huyghebaert, C., Groeseneken, G., Rao, V. R., Bhuwalka, K. K., Heyns, M. M., Collaert, N. & Thean, A. V. Y., 2014 Mar, In : IEEE Transactions on Electron Devices. 61, 3, p. 707-715 9 p., 6727530.

Research output: Contribution to journalArticle

54 Citations (Scopus)

Tensile strained Ge tunnel field-effect transistors: k · p material modeling and numerical device simulation

Kao, K. H., Verhulst, A. S., Van De Put, M., Vandenberghe, W. G., Soree, B., Magnus, W. & De Meyer, K., 2014 Jan 1, In : Journal of Applied Physics. 115, 4, 044505.

Research output: Contribution to journalArticle

30 Citations (Scopus)
2013

A simulation study on process sensitivity of a line tunnel field-effect transistor

Walke, A. M., Vandenberghe, W. G., Kao, K. H., Vandooren, A. & Groeseneken, G., 2013 Feb 15, In : IEEE Transactions on Electron Devices. 60, 3, p. 1019-1027 9 p., 6461086.

Research output: Contribution to journalArticle

4 Citations (Scopus)

Counterdoped pocket thickness optimization of gate-on-source-only tunnel FETs

Kao, K-H., Verhulst, A. S., Vandenberghe, W. G. & De Meyer, K., 2013 Jan 1, In : IEEE Transactions on Electron Devices. 60, 1, p. 6-12 7 p., 6359896.

Research output: Contribution to journalArticle

18 Citations (Scopus)

Erratum: Quantum mechanical performance predictions of p-n-i-n versus pocketed line tunnel field-effect transistors (IEEE Transactions on Electron Devices (2013) 60:7 (2128-2134))

Verreck, D., Verhulst, A. S., Kao, K. H., Vandenberghe, W. G., De Meyer, K. & Groeseneken, G., 2013 Oct 2, In : IEEE Transactions on Electron Devices. 60, 10, 1 p., 6588911.

Research output: Contribution to journalComment/debate

Quantum mechanical performance predictions of p-n-i-n versus pocketed line tunnel field-effect transistors

Verreck, D., Verhulst, A. S., Kao, K. H., Vandenberghe, W. G., De Meyer, K. & Groeseneken, G., 2013 Jun 7, In : IEEE Transactions on Electron Devices. 60, 7, p. 2128-2134 7 p., 6523085.

Research output: Contribution to journalArticle

42 Citations (Scopus)
2012

A model determining optimal doping concentration and material's band gap of tunnel field-effect transistors

Vandenberghe, W. G., Verhulst, A. S., Kao, K. H., Meyer, K. D., Sorée, B., Magnus, W. & Groeseneken, G., 2012 May 7, In : Applied Physics Letters. 100, 19, 193509.

Research output: Contribution to journalArticle

29 Citations (Scopus)

Direct and indirect band-to-band tunneling in germanium-based TFETs

Kao, K-H., Verhulst, A. S., Vandenberghe, W. G., Soree, B., Groeseneken, G. & De Meyer, K., 2012 Feb 1, In : IEEE Transactions on Electron Devices. 59, 2, p. 292-301 10 p., 6096396.

Research output: Contribution to journalArticle

233 Citations (Scopus)

Modeling the impact of junction angles in tunnel field-effect transistors

Kao, K-H., Verhulst, A. S., Vandenberghe, W. G., Sorée, B., Groeseneken, G. & Meyer, K. D., 2012 Mar 1, In : Solid-State Electronics. 69, p. 31-37 7 p.

Research output: Contribution to journalArticle

9 Citations (Scopus)

Optimization of gate-on-source-only tunnel FETs with counter-doped pockets

Kao, K. H., Verhulst, A. S., Vandenberghe, W. G., Sorée, B., Magnus, W., Leonelli, D., Groeseneken, G. & De Meyer, K., 2012 Jul 3, In : IEEE Transactions on Electron Devices. 59, 8, p. 2070-2077 8 p., 6226449.

Research output: Contribution to journalArticle

74 Citations (Scopus)

SiGe band-to-band tunneling calibration based on p-i-n diodes: Fabrication, measurement and simulation

Kao, K. H., Verhulst, A. S., Rooyackers, R., Hikavyy, A., Simoen, E., Arstila, K., Douhard, B., Loo, R., Milenin, A. P., Tolle, J., Dekkers, H., Machkaoutsan, V., Maes, J. W., De Meyer, K., Collaert, N., Heyns, M. M., Huyghebaert, C. & Thean, A., 2012 Dec 1, SiGe, Ge, and Related Compounds 5: Materials, Processing, and Devices. 9 ed. p. 965-970 6 p. (ECS Transactions; vol. 50, no. 9).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)
2011

Si-based tunnel field-effect transistors for low-power nano-electronics

Verhulst, A. S., Vandenberghe, W. G., Leonelli, D., Rooyackers, R., Vandooren, A., Zhuge, J., Kao, K-H., Sorée, B., Magnus, W., Fischetti, M. V., Pourtois, G., Huyghebaert, C., Huang, R., Wang, Y., De Meyer, K., Dehaene, W., Heyns, M. M. & Groeseneken, G., 2011 Dec 1, 69th Device Research Conference, DRC 2011 - Conference Digest. p. 193-196 4 p. 5994494. (Device Research Conference - Conference Digest, DRC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)
2008

Characteristics of PBTI and hot carrier stress for LTPS-TFT with high-κ gate dielectric

Ma, M. W., Chen, C. Y., Su, C. J., Wu, W. C., Wu, Y. H., Kao, K. H., Chao, T. S. & Lei, T. F., 2008 Feb 1, In : IEEE Electron Device Letters. 29, 2, p. 171-173 3 p.

Research output: Contribution to journalArticle

14 Citations (Scopus)

Fluorinated HfO2 gate dielectrics engineering for CMOS by pre-and post-CF4 plasma passivation

Wu, W. C., Lai, C. S., Lee, S. C., Ming-Wen, M., Chao, T. S., Wang, J. C., Hsu, C. W., Chou, P. C., Chen, J. H., Kao, K. H., Lo, W. C., Lu, T. Y., Tay, L. L. & Rowell, N., 2008 Dec 1, 2008 IEEE International Electron Devices Meeting, IEDM 2008. 4796706. (Technical Digest - International Electron Devices Meeting, IEDM).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

High-performance metal-induced laterally crystallized polycrystalline silicon p-channel thin-film transistor with TaN/HfO2 gate stack structure

Ma, M. W., Chao, T. S., Su, C. J., Wu, W. C., Kao, K. H. & Lei, T. F., 2008 Jun 1, In : IEEE Electron Device Letters. 29, 6, p. 592-594 3 p.

Research output: Contribution to journalArticle

3 Citations (Scopus)

Impacts of fluorine ion implantation with low-temperature solid-phase crystallized activation on high-κ LTPS-TFT

Ma, M. W., Chen, C. Y., Su, C. J., Wu, W. C., Wu, Y. H., Yang, T. Y., Kao, K. H., Chao, T. S. & Lei, T. F., 2008 Feb 1, In : IEEE Electron Device Letters. 29, 2, p. 168-170 3 p.

Research output: Contribution to journalArticle

6 Citations (Scopus)

Improvement on performance and reliability of TaN/HfO2 LTPS-TFTs with fluorine implantation

Ma, M. W., Chen, C. Y., Su, C. J., Wu, W. C., Yang, T. Y., Kao, K. H., Chao, T. S. & Lei, T. F., 2008 Mar 1, In : Solid-State Electronics. 52, 3, p. 342-347 6 p.

Research output: Contribution to journalArticle

2 Citations (Scopus)

Reliability mechanisms of LTPS-TFT with HfO2 gate dielectric: PBTI, NBTI, and hot-carrier stress

Ma, M. W., Chen, C. Y., Wu, W. C., Su, C. J., Kao, K. H., Chao, T. S. & Lei, T. F., 2008 May 1, In : IEEE Transactions on Electron Devices. 55, 5, p. 1153-1160 8 p.

Research output: Contribution to journalArticle

33 Citations (Scopus)

X-ray photoelectron spectroscopy energy band alignment of spin-on CoTiO3 high- k dielectric prepared by sol-gel spin coating method

Kao, K. H., Chuang, S. H., Wu, W. C., Chao, T. S., Chen, J. H., Ma, M. W., Gao, R. H. & Chiang, M. Y., 2008 Sep 15, In : Applied Physics Letters. 93, 9, 092907.

Research output: Contribution to journalArticle

3 Citations (Scopus)
2007

Impact of High-K Offset Spacer in 65-nm Node SOI Devices

Ma, M. W., Lei, T. F., Wu, C. H., Wang, S. J., Yang, T. Y., Kao, K. H., Wu, W. C. & Chao, T. S., 2007 Mar 7, In : IEEE Electron Device Letters. 28, 3, p. 238-241 4 p.

Research output: Contribution to journalArticle

24 Citations (Scopus)

Impacts of nitric acid oxidation on low-temperature polycrystalline silicon TFTs with high-κ gate dielectric

Yang, T. Y., Ma, M. W., Kao, K-H., Su, C. J., Chao, T. S. & Lei, T. F., 2007 Dec 1, AD'07 - Proceedings of Asia Display 2007. p. 519-522 4 p. (AD'07 - Proceedings of Asia Display 2007; vol. 1).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Mobility improvement of HfO2 LTPS TFTs with nitrogen implantation

Ma, M. W., Yang, T. Y., Kao, K. H., Su, C. J., Chen, C. Y., Chao, T. S. & Lei, T. F., 2007 Dec 1, AD'07 - Proceedings of Asia Display 2007. p. 674-677 4 p. (AD'07 - Proceedings of Asia Display 2007; vol. 1).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2006

Fringing electric field effect on 65-nm-node fully depleted silicon-on-insulator devices

Ma, M. W., Chao, T. S., Kao, K. H., Huang, J. S. & Lei, T. F., 2006 Sep 7, In : Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers. 45, 9 A, p. 6854-6859 6 p.

Research output: Contribution to journalArticle

3 Citations (Scopus)

High-κ material sidewall with source/drain-to-gate non-overlapped structure for low standby power applications

Ma, M. W., Chao, T. S., Kao, K. H., Huang, J. S. & Lei, T. F., 2006 Nov 15, In : Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers. 45, 11, p. 8656-8658 3 p.

Research output: Contribution to journalArticle