Projects per year
Personal profile
Education
- 2003 PhD, VLSI and Circuit Design, Purdue University, School of Electrical and Computer Engineering, West Lafayette, IN
Research Interests
- CAD for VLSI
- Power-efficient design in both hardware and software
- Reconfigurable computing
Experience
- 1992~present Active Member IEEE
- 1998 Summer Intern Lucent Technology, Holmdel, NJ.;Summer
- 2003~2009 Assistant Professor Dept. of Electrical Engineering, National Cheng Kung University
- 2010~present Associate Professor Dept. of Electrical Engineering, National Cheng Kung University
Expertise related to UN Sustainable Development Goals
In 2015, UN member states agreed to 17 global Sustainable Development Goals (SDGs) to end poverty, protect the planet and ensure prosperity for all. This person’s work contributes towards the following SDG(s):
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Projects
- 20 Finished
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具高安全性且低耗能之物聯網晶片電路及系統之分析、設計及實作-子計畫一：具硬體安全性及能量效益的物聯網微處理器及記憶體設計之研究( II )
21-05-01 → 22-04-30
Project: Research project
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具高安全性且低耗能之物聯網晶片電路及系統之分析、設計及實作-子計畫一：具硬體安全性及能量效益的物聯網微處理器及記憶體設計之研究( I )
20-05-01 → 21-04-30
Project: Research project
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具高安全性且低耗能之物聯網晶片電路及系統之分析、設計與實作-子計畫一：具硬體安全性及能量效益的物聯網微處理器及記憶體設計之研究(2/2)
19-05-01 → 20-04-30
Project: Research project
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具高安全性且低耗能之物聯網晶片電路及系統之分析、設計與實作-子計畫一：具硬體安全性及能量效益的物聯網微處理器及記憶體設計之研究(2/2)
19-05-01 → 20-04-30
Project: Research project
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An Energy-Efficient Conditional Biasing Write Assist with Built-In Time-Based Write-Margin-Tracking for Low-Voltage SRAM
Huang, C. R. & Chiou, L. Y., 2021 Aug, In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 29, 8, p. 1586-1590 5 p., 9448190.Research output: Contribution to journal › Article › peer-review
1 Citation (Scopus) -
A Reliable Near-Threshold Voltage SRAM-Based PUF Utilizing Weight Detection Technique
Chiou, L. Y., Huang, J. Y., Li, C. K. & Tsai, C. C., 2021 Apr 19, 2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 9427315. (2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
2 Citations (Scopus) -
A data-traffic aware dynamic power management for general-purpose graphics processing units
Chiou, L. Y., Yang, C. K. & Chang, C. P., 2019, 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 8702405. (Proceedings - IEEE International Symposium on Circuits and Systems; vol. 2019-May).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
1 Citation (Scopus) -
A reliable delay-based physical unclonable function with dark-bit avoidance
Chiou, L. Y., Wu, C. H. & Wei, P. C., 2019, 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 8702131. (Proceedings - IEEE International Symposium on Circuits and Systems; vol. 2019-May).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
2 Citations (Scopus) -
A variation-tolerant bitline leakage sensing scheme for near-threshold SRAMs
Chiou, L. Y., Huang, C. R., Cheng, C. C., Huang, J. Y. & Ling, W. S., 2019 Apr, 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019. Institute of Electrical and Electronics Engineers Inc., 8741606. (2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution