Engineering
Metal-Oxide-Semiconductor Field-Effect Transistor
100%
Nanowire
54%
Phase Change Memory
31%
Nodes
27%
Field Effect Transistor
27%
Resistive Random Access Memory
23%
Circuit Simulation
19%
Silicon on Insulator
17%
Operating Voltage
15%
Device Performance
14%
System-on-Chip
13%
Cell Design
13%
Circuit Performance
11%
Random Access Memory
11%
Gallium Arsenide
11%
Pyrolysis
11%
Ultrasonics
11%
Two Dimensional
11%
Field-Effect Transistor
11%
Good Performance
10%
Circuit Design
10%
Nanosheet
10%
Electric Power Utilization
10%
Oxide Layer
10%
Low-Temperature
10%
Logic Circuit
9%
Dopants
9%
Indium Gallium Arsenide
9%
Polysilicon
9%
Supply Voltage
9%
Design Power
9%
Nanoscale
9%
Current Output
8%
Tunnel Construction
8%
Gate Length
8%
Scale Length
8%
Current Drive
8%
Metal Oxide Semiconductor
7%
Logic Function
7%
Resistive
7%
3d Simulation
7%
Voltage Scaling
7%
Nitride
7%
Mixed Mode
7%
Heterojunctions
7%
Bipolar Transistor
7%
Gate Capacitance
7%
Breakdown Voltage
7%
Inverter
7%
Channel Region
7%
Material Science
Transistor
68%
Metal-Oxide-Semiconductor Field-Effect Transistor
48%
Electronic Circuit
42%
Silicon
35%
Nanowire
34%
Density
33%
Field Effect Transistor
29%
Electron Mobility
23%
Phase-Change Memory
23%
Doping (Additives)
23%
Capacitance
18%
Resistive Random-Access Memory
15%
Oxide Compound
13%
Spray Pyrolysis
12%
Metal Oxide
11%
Oxide Semiconductor
11%
Aluminum Oxide
11%
Indium Gallium Arsenide
9%
Boron Nitride
7%
Nanoribbon
7%
Titanium Oxide
7%
Nanosheet
7%
Gallium Arsenide
7%
Dielectric Material
7%
Two-Dimensional Material
5%
Carrier Transport
5%
Keyphrases
Fin Field-effect Transistor (FinFET)
16%
MOSFET
13%
InP HEMT
11%
Silicon-on-insulator
11%
InGaP
9%
InGaAs
9%
Gate-all-around
8%
Hybrid Fin
7%
Gallium Arsenide
7%
Delta Doping
7%
Phase Change Random Access Memory (PCRAM)
7%
Device Design
7%
Physics-based Compact Model
7%
Dual-channel
7%
Nanosheet Transistor
7%
Technology Node
7%
Resistive Random Access Memory (ReRAM)
7%
Memory Models
7%
6T-SRAM
7%
Triple-doped
6%
Back Bias
6%
Pass Gate
6%
Bulk FinFET
5%
Double-gate Device
5%
Double Gate
5%
Process Physics
5%
Ultrathin Si
5%
Fully Depleted SOI MOSFET
5%
Microwave Performance
5%
Design Process
5%
Pulsing Scheme
5%
Gate-all-around (GAA) MOSFET
5%
Write Operation
5%
Verilog
5%
Compact Model
5%
