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Research Output 1998 2019

  • 668 Citations
  • 12 h-Index
  • 47 Conference contribution
  • 39 Article
  • 2 Conference article
  • 1 Paper
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Conference contribution
2019

An RRAM with a 2D material embedded double switching layer for neuromorphic computing

Chen, P. A., Ge, R. J., Lee, J. W., Hsu, C. H., Hsu, W-C., Akinwande, D. & Chiang, M-H., 2019 Jan 8, 2018 IEEE 13th Nanotechnology Materials and Devices Conference, NMDC 2018. Institute of Electrical and Electronics Engineers Inc., 8605915. (2018 IEEE 13th Nanotechnology Materials and Devices Conference, NMDC 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

random access memory
oxygen ions
plastic properties
Plasticity
Ions

Atomristors: Memory Effect in Atomically-thin Sheets and Record RF Switches

Ge, R., Wu, X., Kim, M., Chen, P. A., Shi, J., Choi, J., Li, X., Zhang, Y., Chiang, M-H., Lee, J. C. & Akinwande, D., 2019 Jan 16, 2018 IEEE International Electron Devices Meeting, IEDM 2018. Institute of Electrical and Electronics Engineers Inc., p. 22.6.1-22.6.4 8614602. (Technical Digest - International Electron Devices Meeting, IEDM; vol. 2018-December).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

switches
Switches
Data storage equipment
Monolayers
Sulfur

Insights to the scaling impact on back-gate biasing for FD SOI MOSFETs

Chang, M. Y., Wang, L. J. & Chiang, M-H., 2019 Feb 11, 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018. Institute of Electrical and Electronics Engineers Inc., 8640185. (2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

SOI (semiconductors)
field effect transistors
thin bodies
inversions
scaling

Speed Optimization of Vertically Stacked Gate-All-Around MOSFETs with Inner Spacers for Low Power and Ultra-Low Power Applications

Huang, Y. C., Chiang, M-H. & Wang, S-J., 2019 Apr 23, Proceedings of the 20th International Symposium on Quality Electronic Design, ISQED 2019. IEEE Computer Society, p. 231-234 4 p. 8697706. (Proceedings - International Symposium on Quality Electronic Design, ISQED; vol. 2019-March).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Controllability
Leakage currents
Masks
Capacitance
Tuning
2018

An area efficient low-voltage 6-T SRAM cell using stacked silicon nanowires

Huang, Y. C., Chiang, M-H., Wang, S-J. & Gupta, S. K., 2018 Jun 27, ICICDT 2018 - International Conference on IC Design and Technology, Proceedings. Institute of Electrical and Electronics Engineers Inc., p. 117-120 4 p. (ICICDT 2018 - International Conference on IC Design and Technology, Proceedings).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Static random access storage
Nanowires
Doping (additives)
Silicon
Electric potential

A predictive resistive RAM compact model with synaptic behavior for circuit simulations

Lee, J. W., Hsu, C. H. & Chiang, M-H., 2018 Jan 1, TechConnect Briefs 2018 - Informatics, Electronics and Microsystems. Laudon, M., Case, F., Romanowicz, B. & Case, F. (eds.). TechConnect, Vol. 4. p. 232-235 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Circuit simulation
Data storage equipment
Plasticity
RRAM

Body-biasing assisted vmin optimization for 5nm-node multi-Vt FD-SOI 6T-SRAM

Chen, J. Y., Chang, M. Y., Chen, S. H., Lee, J. W. & Chiang, M-H., 2018 May 9, 2018 19th International Symposium on Quality Electronic Design, ISQED 2018. IEEE Computer Society, p. 151-155 5 p. (Proceedings - International Symposium on Quality Electronic Design, ISQED; vol. 2018-March).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Static random access storage
Electric potential
2 Citations (Scopus)

High-density SRAM voltage scaling enabled by inserted-oxide FinFET technology

Wu, Y. T., Chiang, M-H., Chen, J-F., Ding, F., Connelly, D. & Liu, T. J. K., 2018 Mar 7, 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017. Institute of Electrical and Electronics Engineers Inc., p. 1-3 3 p. (2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017; vol. 2018-March).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Static random access storage
Oxides
Electric potential
Threshold voltage
Ion implantation
2017
1 Citation (Scopus)

Gate structure engineering for enhancement-mode AlGaN/GaN MOSHEMT

Liu, H. Y., Lee, C. S., Lin, C. W., Chiang, M-H. & Hsu, W-C., 2017 Aug 1, 75th Annual Device Research Conference, DRC 2017. Institute of Electrical and Electronics Engineers Inc., 7999446. (Device Research Conference - Conference Digest, DRC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

High electron mobility transistors
Threshold voltage
Fluorine
Doping (additives)
Gate dielectrics

Simulation based study of oxygen plasma induced defects on zigzag graphene nanoribbons

Chen, P. A., Lee, J. W., Chiang, M-H. & Hsu, W-C., 2017 Jan 1, ECS Transactions. Bhansali, S., Brankovic, S., Buttry, D. A., Chu, D., Imahori, H., Katayama, H., Leonte, O., Mukerjee, S., Mukundan, R., Oren, Y., Romankiw, L., Sharma, N., Simonian, A., Trulove, P. C., Vaughey, J. T., Winter, M., Bartlett, P. N., Di Noto, V., Doeff, M., Druffel, T., Fenton, J. M., Fergus, J., Fukunaka, Y., Itagaki, M., Koehne, J., Kostecki, R., Lynch, R. P., Milosev, I., Narayan, S. R., Subramanian, V., Tatsuma, T., Wu, N., Chen, Z., Haverhals, L. M., Hesketh, P., Hillier, A. C., Inaba, M., Krumdick, G., Leddy, J., Manivannan, M., Maurice, V., Mitra, S., Muldoon, J., Noel, J., Rajeshwar, K., Subramanian, V. R., Suroviec, A. H., Suto, K., Zangari, G., Allongue, P., Birbilis, N., Boltalina, O. V., Calabrese Barton, S., Chaitanya, V., Chidambaram, D., Hite, J. K., Lee, J. J., Mantz, R. A., Mauzeroll, J., Minteer, S. D., Orazem, M. E., Ramasamy, R. P., Riemer, D. P., Roeper, D., Rohwerder, M., Sailor, M. J., Schwartz, D. T., Staser, J. A., Wu, G., Xu, H., Alkire, R., Anderson, T. J., Bayachou, M., Bocarsly, A. B., Choi, J. W., Innocenti, M., Kilgore, S. H., Kim, D. J., Kulesza, P. J., Lu, Y. C., Marcus, P., Mauter, M., Nicholas, J. D., Pylypenko, S., Rhodes, C., Soleymani, L., Tao, M., Xing, Y., Abbott, A. P., Chin, B. A., Cliffel, D. E., Douglas, E. A., Edstrom, K., Hamada, H., McMurray, H. N., Meng, Y. S., Miller, E. L., Navaei, M., Nonnenmann, S. S., O'Dwyer, C., Pharkya, P., Rotkin, S. V., Rupp, J. L. M., Williams, G., Bock, C., Buchheit, R., Cheek, G. T., Deligianni, H., Johnson, C., Park, J. G., Pintauro, P. N., Smith, K. C., Vanysek, P., Wang, H., Whitacre, J. F., Xiao, J., Carter, M. T., Dimitrov, N., Fransaer, J., Guyomard, D., Lucht, B. L., Nagahara, L., Natishan, P. M., Sekhar, P. K., Smith, D. K., Stafford, G. R., Sundaram, K. B., Vasiljevic, N., Virtanen, S., Wang, W., Wood, D. L. & Yang, J. J. (eds.). 10 ed. Electrochemical Society Inc., p. 463-471 9 p. (ECS Transactions; vol. 80, no. 10).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Nanoribbons
Graphene
Plasmas
Defects
Oxygen

S-shaped gate-all-around MOSFETs for high density design

Huang, Y. C., Wang, S-J. & Chiang, M-H., 2017 Jun 29, Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings. Nassiopoulou, A. G. & Sarafis, P. (eds.). Institute of Electrical and Electronics Engineers Inc., p. 160-163 4 p. 7962566. (Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

layouts
field effect transistors
Schematic diagrams
systems-on-a-chip
Networks (circuits)
2016
1 Citation (Scopus)

An area efficient gate-all-around ring MOSFET

Huang, Y. C., Chiang, M-H. & Wang, S-J., 2016 Sep 27, 2016 IEEE Silicon Nanoelectronics Workshop, SNW 2016. Institute of Electrical and Electronics Engineers Inc., p. 118-119 2 p. 7578011. (2016 IEEE Silicon Nanoelectronics Workshop, SNW 2016).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Transistors
Networks (circuits)
FinFET
System-on-chip
1 Citation (Scopus)

Performance evaluation of stacked gate-all-around MOSFETs at 7 and 10 nm technology nodes

Wu, M. Y. & Chiang, M-H., 2016 May 25, Proceedings of the 17th International Symposium on Quality Electronic Design, ISQED 2016. IEEE Computer Society, p. 169-172 4 p. 7479195. (Proceedings - International Symposium on Quality Electronic Design, ISQED; vol. 2016-May).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Aspect ratio
FinFET
2015
2 Citations (Scopus)

6-T SRAM performance assessment with stacked silicon nanowire MOSFETs

Huang, Y. C., Chiang, M-H., Hsu, W-C. & Cheng, S. Y., 2015 Apr 13, Proceedings of the 16th International Symposium on Quality Electronic Design, ISQED 2015. IEEE Computer Society, p. 610-614 5 p. 7085497. (Proceedings - International Symposium on Quality Electronic Design, ISQED; vol. 2015-April).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Static random access storage
Nanowires
Transistors
Silicon

A steep subthreshold swing technique for gate-all-around SOI MOSFETs

Chen, C. Y., Lin, J. T., Chiang, M-H. & Hsu, W-C., 2015 Jan 1, Advanced CMOS-Compatible Semiconductor Devices 17. Selberherr, S., Omura, Y., Martino, J. A., Raskin, J. P., Ishii, H., Gamiz, F. & Nguyen, B. Y. (eds.). 5 ed. Electrochemical Society Inc., p. 87-92 6 p. (ECS Transactions; vol. 66, no. 5).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Nanowires
Silicon
Computer simulation
Electric potential
Hot Temperature
1 Citation (Scopus)

Comparison of 10 nm GAA vs. FinFET 6-T SRAM performance and yield

Zheng, P., Liao, Y. B., Damrongplasit, N., Chiang, M-H., Hsu, W-C. & Liu, T. J. K., 2015 Dec 4, 2014 Silicon Nanoelectronics Workshop, SNW 2014. Institute of Electrical and Electronics Engineers Inc., 7348585. (2014 Silicon Nanoelectronics Workshop, SNW 2014).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Static random access storage
Electric potential
FinFET
2014
2 Citations (Scopus)

Multi-threshold design methodology of stacked Si-nanowire FETs

Liao, Y. B. & Chiang, M-H., 2014 Jan 30, 2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2014. Institute of Electrical and Electronics Engineers Inc., 7028206. (2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2014).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Field effect transistors
Nanowires
Doping (additives)
Silicon
Substrates
2013
8 Citations (Scopus)

6-T SRAM cell design with gate-all-around silicon nanowire MOSFETs

Liao, Y. B., Chiang, M-H., Damrongplasit, N., Liu, T. J. K. & Hsu, W-C., 2013 Aug 12, 2013 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2013. 6545631. (2013 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2013).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Static random access storage
Nanowires
Silicon
Transistors
Tuning
3 Citations (Scopus)

A compact SPICE model for bipolar resistive switching memory

Hsu, K. H., Ding, W. W. & Chiang, M-H., 2013 Dec 23, 2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013. 6628127. (2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

SPICE
Computer hardware description languages
Data storage equipment
Simulators
Networks (circuits)
9 Citations (Scopus)

Comparative study of process variations in junctionless and conventional double-gate MOSFETs

Chen, C. Y., Lin, J. T. & Chiang, M-H., 2013, IEEE Nanotechnology Materials and Devices Conference, IEEE NMDC 2013. IEEE Computer Society, p. 81-83 3 p. 6707461

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Doping (additives)
Local density approximation
Quantum confinement
Threshold voltage
Probability density function
1 Citation (Scopus)

Microscopic study of random dopant fluctuation in silicon nanowire transistors using 3D simulation

Chen, C. Y., Lin, J. T. & Chiang, M-H., 2013 Mar 13, Proceedings of the 2013 IEEE 5th International Nanoelectronics Conference, INEC 2013. p. 267-270 4 p. 6466019. (Proceedings - Winter Simulation Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Silicon Nanowires
Nanowires
Transistors
Doping (additives)
Fluctuations
4 Citations (Scopus)

Performance advantage and energy saving of triangular-shaped FinFETs

Wu, K., Ding, W. W. & Chiang, M-H., 2013 Dec 31, 2013 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2013. p. 143-146 4 p. 6650595. (International Conference on Simulation of Semiconductor Processes and Devices, SISPAD).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Energy Saving
Triangular
Energy conservation
Leakage currents
Capacitance

Performance comparison of non-planar MOSFETs

Liao, Y. B., Chiang, M-H. & Hsu, W-C., 2013, Technical Proceedings of the 2013 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2013. Vol. 2. p. 9-12 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Static Electricity
Equipment and Supplies
2012

Demonstration of a novel multilevel storage scheme for phase change memory using a parameterized HSPICE model

Chao, D. S., Lien, C. H., Liao, Y. B., Chiang, M-H., Yen, P. H., Chen, M. J., Chiang, P. C. & Tsai, M. J., 2012 Dec 1, China Semiconductor Technology International Conference 2012, CSTIC 2012. 1 ed. p. 1303-1310 8 p. (ECS Transactions; vol. 44, no. 1).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Phase change memory
Pulse code modulation
Demonstrations

Design issues and insights of multi-fin bulk silicon FinFETs

Li, H. & Chiang, M-H., 2012 Jul 16, Proceedings of the 13th International Symposium on Quality Electronic Design, ISQED 2012. p. 723-726 4 p. 6187571. (Proceedings - International Symposium on Quality Electronic Design, ISQED).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Silicon
Substrates
Leakage currents
Aspect ratio
Transistors
2011
3 Citations (Scopus)

A high-density SRAM design technique using silicon nanowire FETs

Liao, Y. B., Chiang, M-H., Kim, K. & Hsu, W-C., 2011 Dec 1, 2011 International Semiconductor Device Research Symposium, ISDRS 2011. 6135407. (2011 International Semiconductor Device Research Symposium, ISDRS 2011).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Static random access storage
Field effect transistors
Nanowires
Wire
Silicon
5 Citations (Scopus)

Optimal device design of FinFETs on a bulk substrate

Liao, Y. B., Hsu, W-C., Chiang, M-H., Li, H., Lin, C. L. & Lai, Y. S., 2011 Sep 26, 4th IEEE International NanoElectronics Conference, INEC 2011. 5991787. (Proceedings - International NanoElectronics Conference, INEC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Leakage currents
Oxides
Substrates
FinFET
1 Citation (Scopus)

Variability study of silicon nanowire FETs

Liao, Y. B., Chiang, M-H., Kim, K. & Hsu, W-C., 2011 Nov 23, Technical Proceedings of the 2011 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2011. p. 46-49 4 p. (Technical Proceedings of the 2011 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2011; vol. 2).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Static random access storage
Field effect transistors
Nanowires
Wire
Silicon
2010
10 Citations (Scopus)

High-performance ultra-low power junctionless nanowire FET on SOI substrate in subthreshold logic application

Chen, C. Y., Lin, J. T., Chiang, M-H. & Kim, K., 2010 Dec 30, 2010 IEEE International SOI Conference, SOI 2010. 5641061. (Proceedings - IEEE International SOI Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Field effect transistors
Nanowires
Scalability
Wire
Computer simulation
3 Citations (Scopus)

Impact of resistance drift on multilevel PCM design

Chiu, Y. H., Liao, Y. B., Chiang, M-H., Lin, C. L., Hsu, W-C., Chiang, P. C., Hsu, Y. Y., Liu, W. H., Sheu, S. S., Su, K. L., Kao, M. J. & Tsai, M. J., 2010, 2010 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2010. p. 20-23 4 p. 5510298

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Pulse code modulation
Phase change memory
Temperature

Pragmatic study of the nanowire FETs with nonideal gate structures

Lin, J. T., Chen, C. Y. & Chiang, M-H., 2010 Oct 22, 2010 Silicon Nanoelectronics Workshop, SNW 2010. 5562568. (2010 Silicon Nanoelectronics Workshop, SNW 2010).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Gates (transistor)
Field effect transistors
Nanowires
Wire
Oxides
2009
9 Citations (Scopus)

Design optimization in write speed of multi-level cell application for phase change memory

Lin, J. T., Liao, Y. B., Chiang, M-H., Chiu, I. H., Lin, C. L., Hsu, W-C., Chiang, P. C., Sheu, S. S., Hsu, Y. Y., Liu, W. H., Su, K. L., Kao, M. J. & Tsai, M. J., 2009 Dec 1, 2009 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2009. p. 525-528 4 p. 5394196. (2009 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2009).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Phase change memory
Pulse code modulation
Quenching
Design optimization
7 Citations (Scopus)

Double-Gate MOSFETs with aymmetric drain underlap: A device-circuit co-design and optimization perspective for SRAM

Goel, A., Gupta, S., Bansal, A., Chiang, M-H. & Roy, K., 2009 Dec 11, 67th Device Research Conference, DRC 2009. p. 57-58 2 p. 5354884. (Device Research Conference - Conference Digest, DRC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Static random access storage
Capacitance
Networks (circuits)
Threshold voltage
Transistors
12 Citations (Scopus)

Operation of multi-level phase change memory using various programming techniques

Lin, J. T., Liao, Y. B., Chiang, M-H. & Hsu, W-C., 2009 Dec 1, 2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009. p. 199-202 4 p. 5166295. (2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Phase change memory
Quenching
2 Citations (Scopus)

Optimal design and performance assessment of extremely-scaled Si nanowire FET on insulator

Chen, C. Y., Liao, Y. B., Chiang, M-H., Kim, K., Hsu, W-C. & Cheng, S. Y., 2009 Dec 28, 2009 IEEE International SOI Conference. 5318741. (Proceedings - IEEE International SOI Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Field effect transistors
Nanowires
Wire
Optimal design
Design optimization
2008
3 Citations (Scopus)

Assessment of novel phase change memory programming techniques

Liao, Y. B., Lin, J. T., Chiang, M-H. & Hsu, W-C., 2008, 2008 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC. 4760662

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Phase change memory
Computer programming
Data storage equipment
3 Citations (Scopus)

Scaling study of nanowire and multi-gate MOSFETs

Chen, C. Y., Liao, Y. B. & Chiang, M-H., 2008, ICSICT 2008 - 2008 9th International Conference on Solid-State and Integrated-Circuit Technology Proceedings. p. 57-60 4 p. 4734462

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Nanowires
nanowires
field effect transistors
scaling
Computer simulation
23 Citations (Scopus)

Temperature-based phase change memory model for pulsing scheme assessment

Liao, Y. B., Lin, J. T. & Chiang, M-H., 2008, Proceedings - 2008 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT. p. 199-202 4 p. 4567278

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Phase change memory
Temperature
Computer hardware description languages
Networks (circuits)
Thermal conductivity
2007
19 Citations (Scopus)

An analytical compact PCM model accounting for partial crystallization

Liao, Y. B., Chen, Y. K. & Chiang, M-H., 2007 Dec 1, IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007. p. 625-628 4 p. 4450202. (IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Phase change memory
Crystallization
Crystalline materials
Computer hardware description languages
Networks (circuits)
2 Citations (Scopus)

Discrete impurity dopant fluctuation in multi-fin FinFFTs: 3D simulation-based study

Lin, J. N., Chan, K. C., Chen, C. Y. & Chiang, M-H., 2007, IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007. p. 577-580 4 p. 4450190

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Doping (additives)
Impurities
Atoms
Computer simulation
FinFET

Optimal design of nanoscale triple-gate devices

Chiang, M-H., Lin, T. N., Kim, K., Chuang, C. T. & Tretz, C., 2007 Dec 1, 2006 IEEE international SOI Conference Proceedings. p. 143-144 2 p. 4062924. (Proceedings - IEEE International SOI Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Citations (Scopus)

Phase change memory modeling using verilog-A

Liao, Y. B., Chen, Y. K. & Chiang, M-H., 2007 Dec 1, 2007 IEEE International Behavioral Modeling and Simulation Workshop, BMAS. p. 159-164 6 p. 4437544. (2007 IEEE International Behavioral Modeling and Simulation Workshop, BMAS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Phase change memory
Computer hardware description languages
Networks (circuits)
Simulators
Data storage equipment
2006
2 Citations (Scopus)

Discrete dopant fluctuation in limited-width FinFETs for VLSI circuit application: A theoretical study

Chiang, M-H., Lin, J. N., Kim, K. & Chuang, C. T., 2006 Dec 1, 2006 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT'06. 1669387. (2006 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT'06).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

VLSI circuits
Doping (additives)
Impurities
Silicon
FinFET

Single polysilicon gate high-density logic using independently-controlled double-gate devices

Chiang, M-H., Kim, K., Chuang, C. T. & Tretz, C., 2006 Dec 1, 2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005. p. 353-356 4 p. 4017604. (2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Polysilicon
Transistors
Logic gates
Logic circuits
Capacitance
2003
3 Citations (Scopus)

A physics-based compact model for nano-scale DG and FD/SOI MOSFETs

Possum, J. G., Ge, L. & Chiang, M-H., 2003 Dec 1, 2003 Nanotechnology Conference and Trade Show - Nanotech 2003. Laudon, M. & Romanowicz, B. (eds.). p. 274-277 4 p. (2003 Nanotechnology Conference and Trade Show - Nanotech 2003; vol. 2).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Physics

Double-gate CMOS evaluation for 45nm technology node

Chiang, M-H., An, J. X., Krivokapic, Z. & Yu, B., 2003, 2003 Nanotechnology Conference and Trade Show - Nanotech 2003. Laudon, M. & Romanowicz, B. (eds.). Vol. 2. p. 326-329 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

SPICE
Circuit simulation
Networks (circuits)
2002
1 Citation (Scopus)

Impact of gate tunneling on the nature of the charge dump current in 100 nm PDSOI technology

Sinha, S., Chiang, M-H. & Pelella, M. M., 2002, IEEE International SOI Conference. p. 41-42 2 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Silicon on insulator technology
Capacitance