• 785 Citations
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1992 …2019
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Research Output 1992 2019

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Article
2019

FETCH: A cloud-native searchable encryption scheme enabling efficient pattern search on encrypted data within cloud services

Chung, S. M., Shieh, M. D. & Chiueh, T. C., 2019 Jan 1, (Accepted/In press) In : International Journal of Communication Systems. e4141.

Research output: Contribution to journalArticle

Cryptography
2018
2 Citations (Scopus)

Low-Complexity VLSI Design of Large Integer Multipliers for Fully Homomorphic Encryption

Ye, J. H. & Shieh, M. D., 2018 Sep, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 26, 9, p. 1727-1736 10 p., 8354942.

Research output: Contribution to journalArticle

Cryptography
Data storage equipment
Inverse transforms
Computer hardware
2015
3 Citations (Scopus)

Depth-reliability-based stereo-matching algorithm and its VLSI architecture design

Yang, D. W., Chu, L. C., Chen, C. W., Wang, J. & Shieh, M. D., 2015 Jun 1, In : IEEE Transactions on Circuits and Systems for Video Technology. 25, 6, p. 1038-1050 13 p., 2361419.

Research output: Contribution to journalArticle

Data storage equipment
Merging
Pixels
Hardware
Bandwidth
23 Citations (Scopus)

Efficient Memory-Addressing Algorithms for FFT Processor Design

Luo, H. F., Liu, Y. J. & Shieh, M-D., 2015 Oct 1, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 23, 10, p. 2162-2172 11 p., 6930760.

Research output: Contribution to journalArticle

Fast Fourier transforms
Data storage equipment
Energy dissipation
Digital video broadcasting (DVB)
Relocation
2014
10 Citations (Scopus)

Scalable montgomery modular multiplication architecture with low-latency and low-memory bandwidth requirement

Lin, W. C., Ye, J. H. & Shieh, M. D., 2014 Feb, In : IEEE Transactions on Computers. 63, 2, p. 475-483 9 p., 6296657.

Research output: Contribution to journalArticle

Montgomery multiplication
Modular multiplication
Latency
Bandwidth
Data storage equipment
2013
4 Citations (Scopus)

Initial settings of Berlekamp-Massey algorithm for efficient hardware implementation

Lu, Y. K. & Shieh, M. D., 2013 Jan 31, In : Electronics Letters. 49, 3, p. 190-191 2 p.

Research output: Contribution to journalArticle

Hardware
Decoding
Computational complexity
Electric power utilization
Costs
6 Citations (Scopus)

Reactivation of spares for off-chip memory repair after die stacking in a 3-D IC with TSVs

Chou, Y. F., Kwai, D. M., Shieh, M. D. & Wu, C. W., 2013 Mar 11, In : IEEE Transactions on Circuits and Systems I: Regular Papers. 60, 9, p. 2343-2351 9 p., 6470720.

Research output: Contribution to journalArticle

Repair
Data storage equipment
Electric fuses
Silicon
Dynamic random access storage
8 Citations (Scopus)

Subspace-based blind channel estimation by separating real and imaginary symbols for cyclic-prefixed single-carrier systems

Fang, S. H., Chen, J. Y., Shieh, M. D. & Lin, J. S., 2013 Dec 1, In : IEEE Transactions on Broadcasting. 59, 4, p. 698-704 7 p., 6615939.

Research output: Contribution to journalArticle

Channel estimation
Impulse response
Binary phase shift keying
Pulse amplitude modulation
2012
3 Citations (Scopus)

Blind channel estimation for cyclic prefix-free orthogonal frequency-division multiplexing systems with particular input symbols

Fang, S. H., Chen, J. Y., Shieh, M-D. & Lin, J. S., 2012 Jan 1, In : IET Communications. 6, 16, p. 2654-2660 7 p.

Research output: Contribution to journalArticle

Channel estimation
Orthogonal frequency division multiplexing
Impulse response
Bit error rate
1 Citation (Scopus)

Low-complexity memory access architectures for quasi-cyclic LDPC decoders

Shieh, M. D., Fang, S. H., Tang, S. C. & Yang, D. W., 2012 Feb, In : IEICE Transactions on Information and Systems. E95-D, 2, p. 549-557 9 p.

Research output: Contribution to journalArticle

Data storage equipment
Computer peripheral equipment
Merging
Decoding
Specifications
4 Citations (Scopus)

Low-power context-based adaptive binary arithmetic encoder using an embedded cache

Lei, S-F., Lo, C. C., Kuo, C. C. & Shieh, M-D., 2012 Jun 1, In : IET Image Processing. 6, 4, p. 309-317 9 p.

Research output: Contribution to journalArticle

Electric power utilization
Throughput
Computational complexity
Pipelines
Data storage equipment
2011

Design and implementation of a low-complexity reed-solomon decoder for optical communication systems

Shieh, M. D. & Lu, Y. K., 2011 Aug, In : IEICE Transactions on Information and Systems. E94-D, 8, p. 1557-1564 8 p.

Research output: Contribution to journalArticle

Optical communication
Communication systems
Throughput
Polynomials
Hardware

Design of high-speed iterative dividers in GF(2m)

Shieh, M. D., Lin, W. C. & Wu, C. M., 2011 May 1, In : Journal of Information Science and Engineering. 27, 3, p. 953-967 15 p.

Research output: Contribution to journalArticle

costs
Cryptography
hardware
Costs
Values
1 Citation (Scopus)
MIMO-OFDM
Multi-core Processor
MIMO systems
Wireless Communication
Fast Fourier transforms
2010
25 Citations (Scopus)

A high-performance unified-field reconfigurable cryptographic processor

Chen, J. H., Shieh, M-D. & Lin, W. C., 2010 Aug 1, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 18, 8, p. 1145-1158 14 p., 5325648.

Research output: Contribution to journalArticle

Cryptography
Firmware
Security of data
Computer programming
Computer hardware
1 Citation (Scopus)

Blind channel estimation for SIMO-OFDM systems without Cyclic Prefix

Fang, S. H., Chen, J. Y., Shieh, M. D. & Lin, J. S., 2010 Jan, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E93-A, 1, p. 339-343 5 p.

Research output: Contribution to journalArticle

Cyclic Prefix
Channel Estimation
Channel estimation
Orthogonal Frequency Division multiplexing (OFDM)
Orthogonal frequency division multiplexing
6 Citations (Scopus)

High-speed low-complexity architecture for reed-solomon decoders

Lu, Y. K. & Shieh, M. D., 2010 Jul, In : IEICE Transactions on Information and Systems. E93-D, 7, p. 1824-1831 8 p.

Research output: Contribution to journalArticle

Hardware
Throughput
Polynomials
Processing
14 Citations (Scopus)

Low-cost FFT processor for DVB-T2 applications

Lin, S. Y., Wey, C. L. & Shieh, M-D., 2010 Nov 1, In : IEEE Transactions on Consumer Electronics. 56, 4, p. 2072-2079 8 p., 5681074.

Research output: Contribution to journalArticle

Fast Fourier transforms
Data storage equipment
Costs
Orthogonal frequency division multiplexing
Electric power utilization
9 Citations (Scopus)

Reconfigurable architecture for entropy decoding and inverse transform in H.264

Lo, C. C., Tsai, S. T. & Shieh, M-D., 2010 Aug 1, In : IEEE Transactions on Consumer Electronics. 56, 3, p. 1670-1676 7 p., 5606311.

Research output: Contribution to journalArticle

Reconfigurable architectures
Inverse transforms
Decoding
Entropy
Reconfigurable hardware
31 Citations (Scopus)

Word-based montgomery modular multiplication algorithm for low-latency scalable architectures

Shieh, M. D. & Lin, W. C., 2010 Jul 6, In : IEEE Transactions on Computers. 59, 8, p. 1145-1151 7 p., 5441286.

Research output: Contribution to journalArticle

Montgomery multiplication
Modular multiplication
Cryptography
Latency
Hardware
2009
3 Citations (Scopus)

An efficient multiplier/divider design for elliptic curve cryptosystem over GF(2m)

Shieh, M-D., Chen, J. H., Lin, W. C. & Wu, C. M., 2009 Dec 1, In : Journal of Information Science and Engineering. 25, 5 SPECIAL ISSUE, p. 1555-1573 19 p.

Research output: Contribution to journalArticle

multiplier
Cryptography
Polynomials
Hardware
Degradation
32 Citations (Scopus)

A new algorithm for high-speed modular multiplication design

Shieh, M-D., Chen, J. H., Lin, W. C. & Wu, H. H., 2009 Sep 25, In : IEEE Transactions on Circuits and Systems I: Regular Papers. 56, 9, p. 2009-2019 11 p.

Research output: Contribution to journalArticle

Cryptography
Hardware

Design of a high-throughput CABAC encoder

Lo, C. C., Zeng, Y. J. & Shieh, M. D., 2009 Jan 1, In : IEICE Transactions on Information and Systems. E92-D, 4, p. 681-688 8 p.

Research output: Contribution to journalArticle

Bins
Throughput
Hardware
Data storage equipment

Efficient reed-solomon decoder design for multi-mode applications

Shieh, M. D., Lu, Y. K. & Chung, S. M., 2009 Dec 1, In : International Journal of Electrical Engineering. 16, 6, p. 503-516 14 p.

Research output: Contribution to journalArticle

Hardware
Network routing
Throughput
Topology
8 Citations (Scopus)

Low-power register-exchange survivor memory architectures for viterbi decoders

Shieh, M-D., Wang, T. P. & Yang, D. W., 2009 Apr 20, In : IET Circuits, Devices and Systems. 3, 2, p. 83-90 8 p.

Research output: Contribution to journalArticle

Memory architecture
Energy dissipation
Data storage equipment
2008
71 Citations (Scopus)

Algorithms of finding the first two minimum values and their hardware implementation

Wey, C. L., Shieh, M-D. & Lin, S. Y., 2008 Dec 1, In : IEEE Transactions on Circuits and Systems I: Regular Papers. 55, 11, p. 3430-3437 8 p.

Research output: Contribution to journalArticle

Hardware
Costs
Sorting
54 Citations (Scopus)

A new modular exponentiation architecture for efficient design of RSA cryptosystem

Shieh, M-D., Chen, J. H., Wu, H. H. & Lin, W. C., 2008 Sep 1, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 16, 9, p. 1151-1161 11 p., 4579747.

Research output: Contribution to journalArticle

Cryptography
Hardware
Communication

Reducing interconnect complexity for efficient path metric memory management in viterbi decoders

Shieh, M. D., Wang, T. P. & Wu, C. M., 2008 Sep, In : IEICE Transactions on Information and Systems. E91-D, 9, p. 2300-2311 12 p.

Research output: Contribution to journalArticle

Data storage equipment
Convolutional codes
Processing
Scheduling
Bandwidth
2006
2 Citations (Scopus)

High-speed design of montgomery tnverse algorithm over GF(2m)

Shieh, M. D., Chen, J. H. & Wu, C. M., 2006 Jan 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E89-A, 2, p. 559-565 7 p.

Research output: Contribution to journalArticle

High Speed
Hardware Implementation
Cryptosystem
Hardware
Hardware Architecture
2005
13 Citations (Scopus)

VLSI architectural design tradeoffs for sliding-window Log-MAP decoders

Wu, C. M., Shieh, M-D., Wu, C. H., Hwang, Y. T. & Chen, J. H., 2005 Apr 1, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 13, 4, p. 439-447 9 p.

Research output: Contribution to journalArticle

Architectural design
Decoding
Mobile radio systems
Turbo codes
Electric power utilization
2004
47 Citations (Scopus)

High-speed, low-complexity systolic designs of novel iterative division algorithms in GF(2m)

Wu, C. H., Wu, C. M., Shieh, M. D. & Hwang, Y. T., 2004 Mar 1, In : IEEE Transactions on Computers. 53, 3, p. 375-380 6 p.

Research output: Contribution to journalArticle

Low Complexity
Division
High Speed
Euclidean algorithm
Critical Path
2003
Digital radio
Decoding
Data storage equipment
Application specific integrated circuits
Computer hardware

Exploring general memory structures in turbo decoders using sliding-window MAP algorithm

Wu, C. M., Shieh, M. D. & Wu, C. H., 2003 Nov, In : IEICE Transactions on Communications. E86-B, 11, p. 3163-3173 11 p.

Research output: Contribution to journalArticle

Decoding
Data storage equipment
Data communication systems
Computational complexity
Signal to noise ratio
Fast Fourier transforms
Data storage equipment
Coloring
Demodulators
Computer hardware
2002
2 Citations (Scopus)

Novel algorithms and VLSI design for division over GF(2m)

Wu, C. H., Wu, C. M., Shieh, M. D. & Hwang, Y. T., 2002 May, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E85-A, 5, p. 1129-1139 11 p.

Research output: Contribution to journalArticle

VLSI Design
Algorithm Design
Division
Wiener-Hopf Equations
Discrete-time
2001
36 Citations (Scopus)

A systematic approach for parallel CRC computations

Shieh, M-D., Sheu, M. H., Chen, C. H. & Lo, H. F., 2001 May 1, In : Journal of Information Science and Engineering. 17, 3, p. 445-461 17 p.

Research output: Contribution to journalArticle

Codes (standards)
redundancy
Redundancy
hardware
Networks (circuits)
2000
2 Citations (Scopus)

High-speed generation of LFSR signatures

Shieh, M. D., Lo, H. F. & Sheu, M. H., 2000 Jan 1, In : Proceedings of the Asian Test Symposium. p. 222-227 6 p.

Research output: Contribution to journalArticle

Compaction
Hardware
Data storage equipment
1999
18 Citations (Scopus)

Design and implementation of a DAB channel decoder

Shieh, M. D., Wu, C. M., Chou, H. H., Chen, M. H. & Liu, C. L., 1999 Aug 1, In : IEEE Transactions on Consumer Electronics. 45, 3, p. 553-562 10 p.

Research output: Contribution to journalArticle

Polysilicon
Data storage equipment
Silicon
Metals
1998
16 Citations (Scopus)

Design of a high-speed square generator

Wey, C. L. & Shieh, M. D., 1998 Dec 1, In : IEEE Transactions on Computers. 47, 9, p. 1021-1026 6 p.

Research output: Contribution to journalArticle

ROM
High Speed
Generator
Table
Look-up Table
1993
3 Citations (Scopus)

Fault effects in asynchronous sequential logic circuits

Shieh, M-D., Wey, C. L. & Fisher, P. D., 1993 Nov 1, In : IEE Proceedings E: Computers and Digital Techniques. 140, 6, p. 327-332 6 p.

Research output: Contribution to journalArticle

Asynchronous sequential logic
Sequential circuits
State assignment