Projects per year
Personal profile
Education
- 2002 PhD, Electronic Research Institute, National Chiao-Tung University
Research Interests
- Computer Aided Integrated Circuits Design
- Mixed-Signal Integrated Circuits Design, Test and Design-for-Testability
Experience
- 2002/10~2003/01 Engineer, SoC Technology Center, Industrial Technology and Research Institute (ITRI), Taiwan.
- 2003/02~2008/07 Assistant Professor, Department of Electrical Engineering, National Cheng Kung University
- 2008/08~2011/07 Associate Professor, Department of Electrical Engineering, National Cheng Kung University
- 2009/01~2012/12 Chair, IEEE Solid-State Circuits Society Tainan Chapter.
- 2011/08~2014/07 Director, Electrical Laboratories, National Cheng Kung University
- 2011/08~present Professor, Department of Electrical Engineering, National Cheng Kung University
Fingerprint Dive into the research topics where Soon-Jyh Chang is active. These topic labels come from the works of this person. Together they form a unique fingerprint.
- 7 Similar Profiles
Digital to analog conversion
Engineering & Materials Science
Networks (circuits)
Engineering & Materials Science
Capacitors
Engineering & Materials Science
Operational amplifiers
Engineering & Materials Science
Electric power utilization
Engineering & Materials Science
Built-in self test
Engineering & Materials Science
Electric potential
Engineering & Materials Science
Clock and data recovery circuits (CDR circuits)
Engineering & Materials Science
Network
Recent external collaboration on country level. Dive into details by clicking on the dots.
Projects 2003 2020
具高安全性且低耗能之物聯網晶片電路及系統之分析、設計及實作-子計畫三：應用於高安全性且低耗能物聯網系統的類比至數位轉換器之研製(2/2)
19-05-01 → 20-04-30
Project: Research project
考量三維晶片平面規畫與除錯之低功耗動態調整電壓與頻率之設計方法-子計畫三：應用於三維晶片之溫度感測與時脈電路設計技術研發
15-08-01 → 16-07-31
Project: Research project
Research Output 1997 2019
A 10-bit 1-GS/s 2x-interleaved timing-skew calibration free SAR ADC
Hu, H. J., Cheng, Y. S. & Chang, S-J., 2019 Jan 1, 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 8702455. (Proceedings - IEEE International Symposium on Circuits and Systems; vol. 2019-May).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
Digital to analog conversion
Calibration
Clocks
Switches
Networks (circuits)
A 2-GS/s 8b flash-SAR time-interleaved ADC with background offset calibration
Cheng, Y. S., Hu, H. J. & Chang, S-J., 2019 Jan 1, 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 8702543. (Proceedings - IEEE International Symposium on Circuits and Systems; vol. 2019-May).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
Calibration
Networks (circuits)
Redundancy
Clocks
A 11-bit 35-MS/s wide input range SAR ADC in 180-nm CMOS process
Luo, W. C., Chang, S-J., Huang, C. P. & Wu, H. S., 2018 Jun 5, 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018. Institute of Electrical and Electronics Engineers Inc., p. 1-4 4 p. (2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
Analog-to-digital Converter
Successive Approximation
Digital to analog conversion
Range of data
Networks (circuits)
2
Citations
(Scopus)
A 12-b 40-MS/s Calibration-Free SAR ADC
Hsu, C. W., Chang, S-J., Huang, C. P., Chang, L. J., Shyu, Y. T., Hou, C. H., Tseng, H. A., Kung, C. Y. & Hu, H. J., 2018 Mar 1, In : IEEE Transactions on Circuits and Systems I: Regular Papers. 65, 3, p. 881-890 10 p.Research output: Contribution to journal › Article
Digital to analog conversion
Calibration
Capacitors
Sampling
Networks (circuits)
A Fast and Jitter-Modulation Free Jitter Tolerance Estimation Technique for Bang-Bang CDRs
Lee, Y. L., Cheng, Y. P., Chang, S-J. & Ting, H. W., 2018 Feb 1, In : IEEE Design and Test. 35, 1, p. 63-73 11 p., 8039277.Research output: Contribution to journal › Article
Clock and data recovery circuits (CDR circuits)
Jitter
Modulation
Thesis
A 0 5-to-3 0 Gb/s Dual Edge Sampling Delay-Locked Loop Based Clock and Data Recovery Circuit
Author: 繼仁, 吳., 2014 Aug 20Supervisor: Chang, S. (Supervisor)
Student thesis: Master's Thesis
A 0 5-to-5 Gbps Continuous Rate Clock and Data Recovery Circuit with Bi-directional Frequency Detection
Author: 彥錡, 陳., 2014 Mar 7Supervisor: Chang, S. (Supervisor)
Student thesis: Master's Thesis
A 10-bit 120-MS/s SAR ADC with Compact Architecture and Noise Suppression Technique
Author: 哲勳, 郭., 2014 Aug 22Supervisor: Chang, S. (Supervisor)
Student thesis: Master's Thesis
A 10-bit 300-MS/s Successive-Approximation Analog-to-Digital Converter with a Pre-amplifier-only Comparator
Author: 恩澤, 寸., 2019Supervisor: Chang, S. (Supervisor)
Student thesis: Master's Thesis
A 10-bit 600-MS/s 2x-Interleaved Timing-Skew Insensitive Successive-Approximation Analog-to-Digital Converter
Author: 桓睿, 胡., 2019Supervisor: Chang, S. (Supervisor)
Student thesis: Master's Thesis