Wirelength-Driven Routability-Aware Die Placement and Package Routing through Better Bump Assignment in the Interposer-Based 3d Ic

Project: Research project

Project Details

Description

With the approach of the 5G era, a modern chip requires faster data transmission and higher signal processing speed. It is highly expected that a three-dimensional integrated circuit (3D IC) can resolve the problems faced by current two-dimensional integrated circuit (2D IC). However, only limited commercial products are implemented in 3D ICs nowadays because most 3D ICs have much higher manufacturing cost but cannot achieve expected performance except the interposer-based 3D IC technology, which is regarded as the most promising solution for the next generation IC. The physical design in an interposer-based 3D IC can be divided into two stages which include the die level stage and the interposer level stage. In the die level stage, each single die can be designed by traditional EDA tools. After all the dies have been manufactured, they are integrated in an interposer, which make the interposer level stage face greater challenges such as determination of the locations of all dies, assignment of the I/O pins of each die to the associated micro-bumps, and the thermal management with TSV and system level. In this project, we will focus on two challenges faced by the interposer-based 3D IC and explore possible solutions: 1. The analytical-based floorplanning methodology which can automatically determine the locations and orientations of dies in an interposer. 2. Bump assignment for the I/O pins within the global view in order to complete routing with shortest wirelength and under the limited number of routing layers in an interposer. The solution space of the interposed-based 3D IC floorplanning problem increases dramatically when more dies are considered since each die has four orientations. However, previous works either use the time-consuming simulated annealing algorithm or the enumeration method to handle this problem, which make their approaches feasible with a small number of dies. Therefore, we try to use the analytical-based floorplanning methodology to resolve the problem, which not only can spread dies over a placement region while optimizing total wirelength in a global view but also can determine the suitable orientations of all dies simultaneously. More importantly, the proposed methodology is very efficient and can handle a large number of dies. Some literature has discussed about the routing problem in the interposer-based 3D IC, but they only focus on the routing problem inside the interposer. They assume that the I/O pins of each die have been assigned to micro-bumps. However, the micro-bump assignment of I/O pins has great impact on the routing result in an interposer. Their methods may not be able to complete routing in a given metal layers of an interposer or require longer wirelength. To resolve this problem, we propose a routing methodology which first assign I/O pins to better micro-bumps by considering the relative locations of dies in an interposer. With a better micro-bump assignment, we can complete routing in a given number of routing layers, furthermore, we can not only get the smaller wirelength but also reduce the iterative times when the routing in an interposer is performed.
StatusFinished
Effective start/end date19-08-0120-07-31

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