0.35-μm asymmetric and symmetric LDD device comparison using a reliability/speed/power methodology

Jone F. Chen; Jiang Tao; Peng Fang; Chenming Hu

doi:10.1109/55.701421

0.35-μm asymmetric and symmetric LDD device comparison using a reliability/speed/power methodology

Jone F. Chen, Jiang Tao, Peng Fang, Chenming Hu

Institute of Microelectronics

Research output: Contribution to journal › Article › peer-review

12 Citations (Scopus)

Abstract

The reliability and performance of NMOSFET asymmetric LDD devices (with no LDD on the source side) are compared with that of conventional LDD devices. The results show that asymmetric LDD devices exhibit higher I _dsat and larger I _sub. To maintain the same hot-carrier lifetime, asymmetric LDD devices must operate at lower V _dd. For the same hot-carrier lifetime, we show that ring oscillators with asymmetric LDD devices can achieve 5% (10% if PMOSFET also had asymmetric LDD) higher speed and 10% lower power.

Original language	English
Pages (from-to)	216-218
Number of pages	3
Journal	IEEE Electron Device Letters
Volume	19
Issue number	7
DOIs	https://doi.org/10.1109/55.701421
Publication status	Published - 1998 Jul

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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10.1109/55.701421

Cite this

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title = "0.35-μm asymmetric and symmetric LDD device comparison using a reliability/speed/power methodology",

abstract = "The reliability and performance of NMOSFET asymmetric LDD devices (with no LDD on the source side) are compared with that of conventional LDD devices. The results show that asymmetric LDD devices exhibit higher I dsat and larger I sub. To maintain the same hot-carrier lifetime, asymmetric LDD devices must operate at lower V dd. For the same hot-carrier lifetime, we show that ring oscillators with asymmetric LDD devices can achieve 5% (10% if PMOSFET also had asymmetric LDD) higher speed and 10% lower power.",

author = "Chen, {Jone F.} and Jiang Tao and Peng Fang and Chenming Hu",

note = "Funding Information: Manuscript received November 11, 1997; revised March 5, 1998. The research at UC Berkeley was supported in part by ONR under Contract FDN00014-96-1-0369. J. F. Chen and C. Hu are with the Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA 94720 USA. J. Tao and P. Feng are with Advanced Micro Devices, Inc., Sunnyvale, CA 94088 USA. Publisher Item Identifier S 0741-3106(98)04765-X.",

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T1 - 0.35-μm asymmetric and symmetric LDD device comparison using a reliability/speed/power methodology

AU - Chen, Jone F.

AU - Tao, Jiang

AU - Fang, Peng

AU - Hu, Chenming

N1 - Funding Information: Manuscript received November 11, 1997; revised March 5, 1998. The research at UC Berkeley was supported in part by ONR under Contract FDN00014-96-1-0369. J. F. Chen and C. Hu are with the Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA 94720 USA. J. Tao and P. Feng are with Advanced Micro Devices, Inc., Sunnyvale, CA 94088 USA. Publisher Item Identifier S 0741-3106(98)04765-X.

PY - 1998/7

Y1 - 1998/7

N2 - The reliability and performance of NMOSFET asymmetric LDD devices (with no LDD on the source side) are compared with that of conventional LDD devices. The results show that asymmetric LDD devices exhibit higher I dsat and larger I sub. To maintain the same hot-carrier lifetime, asymmetric LDD devices must operate at lower V dd. For the same hot-carrier lifetime, we show that ring oscillators with asymmetric LDD devices can achieve 5% (10% if PMOSFET also had asymmetric LDD) higher speed and 10% lower power.

AB - The reliability and performance of NMOSFET asymmetric LDD devices (with no LDD on the source side) are compared with that of conventional LDD devices. The results show that asymmetric LDD devices exhibit higher I dsat and larger I sub. To maintain the same hot-carrier lifetime, asymmetric LDD devices must operate at lower V dd. For the same hot-carrier lifetime, we show that ring oscillators with asymmetric LDD devices can achieve 5% (10% if PMOSFET also had asymmetric LDD) higher speed and 10% lower power.

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0.35-μm asymmetric and symmetric LDD device comparison using a reliability/speed/power methodology

Abstract

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