0.75-V subthreshold CMOS logic using dynamic substrate bias

Yu Cherng Hung, Bin Da Liu

Research output: Contribution to conferencePaper

1 Citation (Scopus)

Abstract

In this paper, a 0.75-V CMOS logic operated in sub threshold region is proposed. Based on dynamic substrate bias, the supply voltage of the circuit is effectively reduced. Using UMC 0.5-μm CMOS technology, the logic circuits are verified by inverter function, NOR gate, exclusive OR gate, full adder, and ring oscillator. Including I/O pad capacitance, the results of the chip measurement show that the response time of this circuit is order of 100 μs under 0.75-V supply.

Original languageEnglish
Pages345-348
Number of pages4
Publication statusPublished - 2004 Dec 1
Event2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology - Tainan, Taiwan
Duration: 2004 Dec 62004 Dec 9

Other

Other2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology
CountryTaiwan
CityTainan
Period04-12-0604-12-09

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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  • Cite this

    Hung, Y. C., & Liu, B. D. (2004). 0.75-V subthreshold CMOS logic using dynamic substrate bias. 345-348. Paper presented at 2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology, Tainan, Taiwan.