1-V bulk-driven CMOS analog programmable winner-takes-all circuit

Yu Cherng Hung; Bin Da Liu; Chung Yang Tsai

doi:10.1007/s10470-006-8448-3

1-V bulk-driven CMOS analog programmable winner-takes-all circuit

Yu Cherng Hung, Bin Da Liu, Chung Yang Tsai

Department of Electrical Engineering

Research output: Contribution to journal › Article › peer-review

7 Citations (Scopus)

Abstract

In this paper, a 1-V bulk-driven analog winner-takes-all circuit with programmable k-winners capability is proposed. By presetting a set of binary bits, the desired k-winners-take-all or k-losers-take-all function is programmable. The proposed upward-and-downward searching greatly improves the response time. The chip has been fabricated with a 0.25-μm CMOS technology. Simulated results show that the response time of the winner-takes-all circuit is 50 μs under 5-mV identified resolution. The input range is approximately to be rail-to-rail.

Original language	English
Pages (from-to)	53-61
Number of pages	9
Journal	Analog Integrated Circuits and Signal Processing
Volume	49
Issue number	1
DOIs	https://doi.org/10.1007/s10470-006-8448-3
Publication status	Published - 2006 Oct

All Science Journal Classification (ASJC) codes

Signal Processing
Hardware and Architecture
Surfaces, Coatings and Films

Access to Document

10.1007/s10470-006-8448-3

Cite this

@article{6d34d83415e1487c867fb00237ad80c3,

title = "1-V bulk-driven CMOS analog programmable winner-takes-all circuit",

abstract = "In this paper, a 1-V bulk-driven analog winner-takes-all circuit with programmable k-winners capability is proposed. By presetting a set of binary bits, the desired k-winners-take-all or k-losers-take-all function is programmable. The proposed upward-and-downward searching greatly improves the response time. The chip has been fabricated with a 0.25-μm CMOS technology. Simulated results show that the response time of the winner-takes-all circuit is 50 μs under 5-mV identified resolution. The input range is approximately to be rail-to-rail.",

author = "Hung, {Yu Cherng} and Liu, {Bin Da} and Tsai, {Chung Yang}",

note = "Funding Information: ∗This work was in part supported by the Chip Implementation Center and the MOE Program of Promoting Academic Excellence of Universities under the Grant EX-93-E-FA09-5-4.",

year = "2006",

month = oct,

doi = "10.1007/s10470-006-8448-3",

language = "English",

volume = "49",

pages = "53--61",

journal = "Analog Integrated Circuits and Signal Processing",

issn = "0925-1030",

publisher = "Springer Netherlands",

number = "1",

}

TY - JOUR

T1 - 1-V bulk-driven CMOS analog programmable winner-takes-all circuit

AU - Hung, Yu Cherng

AU - Liu, Bin Da

AU - Tsai, Chung Yang

N1 - Funding Information: ∗This work was in part supported by the Chip Implementation Center and the MOE Program of Promoting Academic Excellence of Universities under the Grant EX-93-E-FA09-5-4.

PY - 2006/10

Y1 - 2006/10

N2 - In this paper, a 1-V bulk-driven analog winner-takes-all circuit with programmable k-winners capability is proposed. By presetting a set of binary bits, the desired k-winners-take-all or k-losers-take-all function is programmable. The proposed upward-and-downward searching greatly improves the response time. The chip has been fabricated with a 0.25-μm CMOS technology. Simulated results show that the response time of the winner-takes-all circuit is 50 μs under 5-mV identified resolution. The input range is approximately to be rail-to-rail.

AB - In this paper, a 1-V bulk-driven analog winner-takes-all circuit with programmable k-winners capability is proposed. By presetting a set of binary bits, the desired k-winners-take-all or k-losers-take-all function is programmable. The proposed upward-and-downward searching greatly improves the response time. The chip has been fabricated with a 0.25-μm CMOS technology. Simulated results show that the response time of the winner-takes-all circuit is 50 μs under 5-mV identified resolution. The input range is approximately to be rail-to-rail.

UR - http://www.scopus.com/inward/record.url?scp=33747159876&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=33747159876&partnerID=8YFLogxK

U2 - 10.1007/s10470-006-8448-3

DO - 10.1007/s10470-006-8448-3

M3 - Article

AN - SCOPUS:33747159876

VL - 49

SP - 53

EP - 61

JO - Analog Integrated Circuits and Signal Processing

JF - Analog Integrated Circuits and Signal Processing

SN - 0925-1030

IS - 1

ER -

1-V bulk-driven CMOS analog programmable winner-takes-all circuit

Abstract

All Science Journal Classification (ASJC) codes

Access to Document

Other files and links

Fingerprint

Cite this