Abstract
In this paper, a 1-V bulk-driven analog winner-takes-all circuit with programmable k-winners capability is proposed. By presetting a set of binary bits, the desired k-winners-take-all or k-losers-take-all function is programmable. The proposed upward-and-downward searching greatly improves the response time. The chip has been fabricated with a 0.25-μm CMOS technology. Simulated results show that the response time of the winner-takes-all circuit is 50 μs under 5-mV identified resolution. The input range is approximately to be rail-to-rail.
| Original language | English |
|---|---|
| Pages (from-to) | 53-61 |
| Number of pages | 9 |
| Journal | Analog Integrated Circuits and Signal Processing |
| Volume | 49 |
| Issue number | 1 |
| DOIs | |
| Publication status | Published - 2006 Oct 1 |
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All Science Journal Classification (ASJC) codes
- Signal Processing
- Hardware and Architecture
- Surfaces, Coatings and Films
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1-V bulk-driven CMOS analog programmable winner-takes-all circuit. / Hung, Yu Cherng; Liu, Bin-Da; Tsai, Chung Yang.
In: Analog Integrated Circuits and Signal Processing, Vol. 49, No. 1, 01.10.2006, p. 53-61.Research output: Contribution to journal › Article
TY - JOUR
T1 - 1-V bulk-driven CMOS analog programmable winner-takes-all circuit
AU - Hung, Yu Cherng
AU - Liu, Bin-Da
AU - Tsai, Chung Yang
PY - 2006/10/1
Y1 - 2006/10/1
N2 - In this paper, a 1-V bulk-driven analog winner-takes-all circuit with programmable k-winners capability is proposed. By presetting a set of binary bits, the desired k-winners-take-all or k-losers-take-all function is programmable. The proposed upward-and-downward searching greatly improves the response time. The chip has been fabricated with a 0.25-μm CMOS technology. Simulated results show that the response time of the winner-takes-all circuit is 50 μs under 5-mV identified resolution. The input range is approximately to be rail-to-rail.
AB - In this paper, a 1-V bulk-driven analog winner-takes-all circuit with programmable k-winners capability is proposed. By presetting a set of binary bits, the desired k-winners-take-all or k-losers-take-all function is programmable. The proposed upward-and-downward searching greatly improves the response time. The chip has been fabricated with a 0.25-μm CMOS technology. Simulated results show that the response time of the winner-takes-all circuit is 50 μs under 5-mV identified resolution. The input range is approximately to be rail-to-rail.
UR - http://www.scopus.com/inward/record.url?scp=33747159876&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=33747159876&partnerID=8YFLogxK
U2 - 10.1007/s10470-006-8448-3
DO - 10.1007/s10470-006-8448-3
M3 - Article
AN - SCOPUS:33747159876
VL - 49
SP - 53
EP - 61
JO - Analog Integrated Circuits and Signal Processing
JF - Analog Integrated Circuits and Signal Processing
SN - 0925-1030
IS - 1
ER -