Abstract
A 1-V analog CMOS winner-take-all circuit with programmable k-winner-take-all and k-loser-take-all capabilities is proposed. The proposed up-and-down searching greatly improves the response time. By setting binary signals, the desired k-winner-take-all function or k-loser-take-all function is achieved, without modifying circuit structure. The circuit is verified by TSMC 0.25-μm CMOS technology. The results of post-layout simulation show that the response time of this circuit is 50 μs under 5-mV identified resolution. The dynamic range allows to be rail-to-rail input.
| Original language | English |
|---|---|
| Title of host publication | Proceedings of 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03 |
| Pages | 337-340 |
| Number of pages | 4 |
| DOIs | |
| Publication status | Published - 2003 Dec 1 |
| Event | 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03 - Nanjing, China Duration: 2003 Dec 14 → 2003 Dec 17 |
Publication series
| Name | Proceedings of 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03 |
|---|---|
| Volume | 1 |
Other
| Other | 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03 |
|---|---|
| Country | China |
| City | Nanjing |
| Period | 03-12-14 → 03-12-17 |
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All Science Journal Classification (ASJC) codes
- Signal Processing
- Computer Networks and Communications
Cite this
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1-V rail-to-rail analog CMOS programmable winner-take-all chip with two-side searching capability for neurocomputing applications. / Hung, Yu Cherng; Tsai, Chung Yang; Liu, Bin Da.
Proceedings of 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03. 2003. p. 337-340 1279278 (Proceedings of 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03; Vol. 1).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - 1-V rail-to-rail analog CMOS programmable winner-take-all chip with two-side searching capability for neurocomputing applications
AU - Hung, Yu Cherng
AU - Tsai, Chung Yang
AU - Liu, Bin Da
PY - 2003/12/1
Y1 - 2003/12/1
N2 - A 1-V analog CMOS winner-take-all circuit with programmable k-winner-take-all and k-loser-take-all capabilities is proposed. The proposed up-and-down searching greatly improves the response time. By setting binary signals, the desired k-winner-take-all function or k-loser-take-all function is achieved, without modifying circuit structure. The circuit is verified by TSMC 0.25-μm CMOS technology. The results of post-layout simulation show that the response time of this circuit is 50 μs under 5-mV identified resolution. The dynamic range allows to be rail-to-rail input.
AB - A 1-V analog CMOS winner-take-all circuit with programmable k-winner-take-all and k-loser-take-all capabilities is proposed. The proposed up-and-down searching greatly improves the response time. By setting binary signals, the desired k-winner-take-all function or k-loser-take-all function is achieved, without modifying circuit structure. The circuit is verified by TSMC 0.25-μm CMOS technology. The results of post-layout simulation show that the response time of this circuit is 50 μs under 5-mV identified resolution. The dynamic range allows to be rail-to-rail input.
UR - http://www.scopus.com/inward/record.url?scp=33747160016&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=33747160016&partnerID=8YFLogxK
U2 - 10.1109/ICNNSP.2003.1279278
DO - 10.1109/ICNNSP.2003.1279278
M3 - Conference contribution
AN - SCOPUS:33747160016
SN - 0780377028
SN - 9780780377028
T3 - Proceedings of 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03
SP - 337
EP - 340
BT - Proceedings of 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03
ER -