1-V rail-to-rail analog CMOS programmable winner-take-all chip with two-side searching capability for neurocomputing applications

Yu Cherng Hung, Chung Yang Tsai, Bin Da Liu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

A 1-V analog CMOS winner-take-all circuit with programmable k-winner-take-all and k-loser-take-all capabilities is proposed. The proposed up-and-down searching greatly improves the response time. By setting binary signals, the desired k-winner-take-all function or k-loser-take-all function is achieved, without modifying circuit structure. The circuit is verified by TSMC 0.25-μm CMOS technology. The results of post-layout simulation show that the response time of this circuit is 50 μs under 5-mV identified resolution. The dynamic range allows to be rail-to-rail input.

Original languageEnglish
Title of host publicationProceedings of 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03
Pages337-340
Number of pages4
DOIs
Publication statusPublished - 2003 Dec 1
Event2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03 - Nanjing, China
Duration: 2003 Dec 142003 Dec 17

Publication series

NameProceedings of 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03
Volume1

Other

Other2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03
CountryChina
CityNanjing
Period03-12-1403-12-17

Fingerprint

Rails
Networks (circuits)

All Science Journal Classification (ASJC) codes

  • Signal Processing
  • Computer Networks and Communications

Cite this

Hung, Y. C., Tsai, C. Y., & Liu, B. D. (2003). 1-V rail-to-rail analog CMOS programmable winner-take-all chip with two-side searching capability for neurocomputing applications. In Proceedings of 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03 (pp. 337-340). [1279278] (Proceedings of 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03; Vol. 1). https://doi.org/10.1109/ICNNSP.2003.1279278
Hung, Yu Cherng ; Tsai, Chung Yang ; Liu, Bin Da. / 1-V rail-to-rail analog CMOS programmable winner-take-all chip with two-side searching capability for neurocomputing applications. Proceedings of 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03. 2003. pp. 337-340 (Proceedings of 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03).
@inproceedings{c87434696fbb473fa17d0c2e0d27602a,
title = "1-V rail-to-rail analog CMOS programmable winner-take-all chip with two-side searching capability for neurocomputing applications",
abstract = "A 1-V analog CMOS winner-take-all circuit with programmable k-winner-take-all and k-loser-take-all capabilities is proposed. The proposed up-and-down searching greatly improves the response time. By setting binary signals, the desired k-winner-take-all function or k-loser-take-all function is achieved, without modifying circuit structure. The circuit is verified by TSMC 0.25-μm CMOS technology. The results of post-layout simulation show that the response time of this circuit is 50 μs under 5-mV identified resolution. The dynamic range allows to be rail-to-rail input.",
author = "Hung, {Yu Cherng} and Tsai, {Chung Yang} and Liu, {Bin Da}",
year = "2003",
month = "12",
day = "1",
doi = "10.1109/ICNNSP.2003.1279278",
language = "English",
isbn = "0780377028",
series = "Proceedings of 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03",
pages = "337--340",
booktitle = "Proceedings of 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03",

}

Hung, YC, Tsai, CY & Liu, BD 2003, 1-V rail-to-rail analog CMOS programmable winner-take-all chip with two-side searching capability for neurocomputing applications. in Proceedings of 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03., 1279278, Proceedings of 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03, vol. 1, pp. 337-340, 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03, Nanjing, China, 03-12-14. https://doi.org/10.1109/ICNNSP.2003.1279278

1-V rail-to-rail analog CMOS programmable winner-take-all chip with two-side searching capability for neurocomputing applications. / Hung, Yu Cherng; Tsai, Chung Yang; Liu, Bin Da.

Proceedings of 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03. 2003. p. 337-340 1279278 (Proceedings of 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03; Vol. 1).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - 1-V rail-to-rail analog CMOS programmable winner-take-all chip with two-side searching capability for neurocomputing applications

AU - Hung, Yu Cherng

AU - Tsai, Chung Yang

AU - Liu, Bin Da

PY - 2003/12/1

Y1 - 2003/12/1

N2 - A 1-V analog CMOS winner-take-all circuit with programmable k-winner-take-all and k-loser-take-all capabilities is proposed. The proposed up-and-down searching greatly improves the response time. By setting binary signals, the desired k-winner-take-all function or k-loser-take-all function is achieved, without modifying circuit structure. The circuit is verified by TSMC 0.25-μm CMOS technology. The results of post-layout simulation show that the response time of this circuit is 50 μs under 5-mV identified resolution. The dynamic range allows to be rail-to-rail input.

AB - A 1-V analog CMOS winner-take-all circuit with programmable k-winner-take-all and k-loser-take-all capabilities is proposed. The proposed up-and-down searching greatly improves the response time. By setting binary signals, the desired k-winner-take-all function or k-loser-take-all function is achieved, without modifying circuit structure. The circuit is verified by TSMC 0.25-μm CMOS technology. The results of post-layout simulation show that the response time of this circuit is 50 μs under 5-mV identified resolution. The dynamic range allows to be rail-to-rail input.

UR - http://www.scopus.com/inward/record.url?scp=33747160016&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=33747160016&partnerID=8YFLogxK

U2 - 10.1109/ICNNSP.2003.1279278

DO - 10.1109/ICNNSP.2003.1279278

M3 - Conference contribution

AN - SCOPUS:33747160016

SN - 0780377028

SN - 9780780377028

T3 - Proceedings of 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03

SP - 337

EP - 340

BT - Proceedings of 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03

ER -

Hung YC, Tsai CY, Liu BD. 1-V rail-to-rail analog CMOS programmable winner-take-all chip with two-side searching capability for neurocomputing applications. In Proceedings of 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03. 2003. p. 337-340. 1279278. (Proceedings of 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03). https://doi.org/10.1109/ICNNSP.2003.1279278