1-V rail-to-rail analog CMOS programmable winner-take-all chip with two-side searching capability for neurocomputing applications

Yu Cherng Hung; Chung Yang Tsai; Bin Da Liu

doi:10.1109/ICNNSP.2003.1279278

1-V rail-to-rail analog CMOS programmable winner-take-all chip with two-side searching capability for neurocomputing applications

Yu Cherng Hung, Chung Yang Tsai, Bin Da Liu

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

5 Citations (Scopus)

Abstract

A 1-V analog CMOS winner-take-all circuit with programmable k-winner-take-all and k-loser-take-all capabilities is proposed. The proposed up-and-down searching greatly improves the response time. By setting binary signals, the desired k-winner-take-all function or k-loser-take-all function is achieved, without modifying circuit structure. The circuit is verified by TSMC 0.25-μm CMOS technology. The results of post-layout simulation show that the response time of this circuit is 50 μs under 5-mV identified resolution. The dynamic range allows to be rail-to-rail input.

Original language	English
Title of host publication	Proceedings of 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03
Pages	337-340
Number of pages	4
DOIs	https://doi.org/10.1109/ICNNSP.2003.1279278
Publication status	Published - 2003
Event	2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03 - Nanjing, China Duration: 2003 Dec 14 → 2003 Dec 17

Publication series

Name	Proceedings of 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03
Volume	1

Other

Other	2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03
Country/Territory	China
City	Nanjing
Period	03-12-14 → 03-12-17

All Science Journal Classification (ASJC) codes

Signal Processing
Computer Networks and Communications

Access to Document

10.1109/ICNNSP.2003.1279278

Cite this

Hung, Y. C., Tsai, C. Y., & Liu, B. D. (2003). 1-V rail-to-rail analog CMOS programmable winner-take-all chip with two-side searching capability for neurocomputing applications. In Proceedings of 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03 (pp. 337-340). [1279278] (Proceedings of 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03; Vol. 1). https://doi.org/10.1109/ICNNSP.2003.1279278

Hung, Yu Cherng ; Tsai, Chung Yang ; Liu, Bin Da. / 1-V rail-to-rail analog CMOS programmable winner-take-all chip with two-side searching capability for neurocomputing applications. Proceedings of 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03. 2003. pp. 337-340 (Proceedings of 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03).

@inproceedings{c87434696fbb473fa17d0c2e0d27602a,

title = "1-V rail-to-rail analog CMOS programmable winner-take-all chip with two-side searching capability for neurocomputing applications",

abstract = "A 1-V analog CMOS winner-take-all circuit with programmable k-winner-take-all and k-loser-take-all capabilities is proposed. The proposed up-and-down searching greatly improves the response time. By setting binary signals, the desired k-winner-take-all function or k-loser-take-all function is achieved, without modifying circuit structure. The circuit is verified by TSMC 0.25-μm CMOS technology. The results of post-layout simulation show that the response time of this circuit is 50 μs under 5-mV identified resolution. The dynamic range allows to be rail-to-rail input.",

author = "Hung, {Yu Cherng} and Tsai, {Chung Yang} and Liu, {Bin Da}",

note = "Copyright: Copyright 2011 Elsevier B.V., All rights reserved.; 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03 ; Conference date: 14-12-2003 Through 17-12-2003",

year = "2003",

doi = "10.1109/ICNNSP.2003.1279278",

language = "English",

isbn = "0780377028",

series = "Proceedings of 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03",

pages = "337--340",

booktitle = "Proceedings of 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03",

}

Hung, YC, Tsai, CY & Liu, BD 2003, 1-V rail-to-rail analog CMOS programmable winner-take-all chip with two-side searching capability for neurocomputing applications. in Proceedings of 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03., 1279278, Proceedings of 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03, vol. 1, pp. 337-340, 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03, Nanjing, China, 03-12-14. https://doi.org/10.1109/ICNNSP.2003.1279278

1-V rail-to-rail analog CMOS programmable winner-take-all chip with two-side searching capability for neurocomputing applications. / Hung, Yu Cherng; Tsai, Chung Yang; Liu, Bin Da.

Proceedings of 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03. 2003. p. 337-340 1279278 (Proceedings of 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03; Vol. 1).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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N2 - A 1-V analog CMOS winner-take-all circuit with programmable k-winner-take-all and k-loser-take-all capabilities is proposed. The proposed up-and-down searching greatly improves the response time. By setting binary signals, the desired k-winner-take-all function or k-loser-take-all function is achieved, without modifying circuit structure. The circuit is verified by TSMC 0.25-μm CMOS technology. The results of post-layout simulation show that the response time of this circuit is 50 μs under 5-mV identified resolution. The dynamic range allows to be rail-to-rail input.

AB - A 1-V analog CMOS winner-take-all circuit with programmable k-winner-take-all and k-loser-take-all capabilities is proposed. The proposed up-and-down searching greatly improves the response time. By setting binary signals, the desired k-winner-take-all function or k-loser-take-all function is achieved, without modifying circuit structure. The circuit is verified by TSMC 0.25-μm CMOS technology. The results of post-layout simulation show that the response time of this circuit is 50 μs under 5-mV identified resolution. The dynamic range allows to be rail-to-rail input.

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Hung YC, Tsai CY, Liu BD. 1-V rail-to-rail analog CMOS programmable winner-take-all chip with two-side searching capability for neurocomputing applications. In Proceedings of 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03. 2003. p. 337-340. 1279278. (Proceedings of 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03). https://doi.org/10.1109/ICNNSP.2003.1279278

1-V rail-to-rail analog CMOS programmable winner-take-all chip with two-side searching capability for neurocomputing applications

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