TY - GEN
T1 - 1-V rail-to-rail analog CMOS programmable winner-take-all chip with two-side searching capability for neurocomputing applications
AU - Hung, Yu Cherng
AU - Tsai, Chung Yang
AU - Liu, Bin Da
N1 - Copyright:
Copyright 2011 Elsevier B.V., All rights reserved.
PY - 2003
Y1 - 2003
N2 - A 1-V analog CMOS winner-take-all circuit with programmable k-winner-take-all and k-loser-take-all capabilities is proposed. The proposed up-and-down searching greatly improves the response time. By setting binary signals, the desired k-winner-take-all function or k-loser-take-all function is achieved, without modifying circuit structure. The circuit is verified by TSMC 0.25-μm CMOS technology. The results of post-layout simulation show that the response time of this circuit is 50 μs under 5-mV identified resolution. The dynamic range allows to be rail-to-rail input.
AB - A 1-V analog CMOS winner-take-all circuit with programmable k-winner-take-all and k-loser-take-all capabilities is proposed. The proposed up-and-down searching greatly improves the response time. By setting binary signals, the desired k-winner-take-all function or k-loser-take-all function is achieved, without modifying circuit structure. The circuit is verified by TSMC 0.25-μm CMOS technology. The results of post-layout simulation show that the response time of this circuit is 50 μs under 5-mV identified resolution. The dynamic range allows to be rail-to-rail input.
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U2 - 10.1109/ICNNSP.2003.1279278
DO - 10.1109/ICNNSP.2003.1279278
M3 - Conference contribution
AN - SCOPUS:33747160016
SN - 0780377028
SN - 9780780377028
T3 - Proceedings of 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03
SP - 337
EP - 340
BT - Proceedings of 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03
T2 - 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03
Y2 - 14 December 2003 through 17 December 2003
ER -