1-V rail-to-rail analog CMOS programmable winner-take-all chip with two-side searching capability for neurocomputing applications

Yu Cherng Hung, Chung Yang Tsai, Bin Da Liu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

A 1-V analog CMOS winner-take-all circuit with programmable k-winner-take-all and k-loser-take-all capabilities is proposed. The proposed up-and-down searching greatly improves the response time. By setting binary signals, the desired k-winner-take-all function or k-loser-take-all function is achieved, without modifying circuit structure. The circuit is verified by TSMC 0.25-μm CMOS technology. The results of post-layout simulation show that the response time of this circuit is 50 μs under 5-mV identified resolution. The dynamic range allows to be rail-to-rail input.

Original languageEnglish
Title of host publicationProceedings of 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03
Pages337-340
Number of pages4
DOIs
Publication statusPublished - 2003
Event2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03 - Nanjing, China
Duration: 2003 Dec 142003 Dec 17

Publication series

NameProceedings of 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03
Volume1

Other

Other2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03
CountryChina
CityNanjing
Period03-12-1403-12-17

All Science Journal Classification (ASJC) codes

  • Signal Processing
  • Computer Networks and Communications

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