10-bit 30-MS/s SAR ADC using a switchback switching method

Guan Ying Huang, Soon Jyh Chang, Chun Cheng Liu, Ying Zu Lin

Research output: Contribution to journalArticle

59 Citations (Scopus)

Abstract

This brief presents a 10-bit 30-MS/s successive-approximation-register analog-to-digital converter (ADC) that uses a power efficient switchback switching method. With respect to the monotonic switching method, the input common-mode voltage variation reduces which improves the dynamic offset and the parasitic capacitance variation of the comparator. The proposed switchback switching method does not consume any power at the first digital-to-analog converter switching, which can reduce the power consumption and design effort of the reference buffer. The prototype was fabricated in a 90-nm 1P9M CMOS technology. At 1-V supply and 30 MS/s, the ADC achieves an sequenced neighbor double reservation of 56.89 dB and consumes 0.98 mW, resulting in a figure-of-merit (FOM) of 57 fJ/conversion-step. The ADC core occupies an active area of only 190×,525 μm2.

Original languageEnglish
Article number6172687
Pages (from-to)584-588
Number of pages5
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume21
Issue number3
DOIs
Publication statusPublished - 2013 Mar 11

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Digital to analog conversion
Electric power utilization
Capacitance
Electric potential

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Huang, Guan Ying ; Chang, Soon Jyh ; Liu, Chun Cheng ; Lin, Ying Zu. / 10-bit 30-MS/s SAR ADC using a switchback switching method. In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2013 ; Vol. 21, No. 3. pp. 584-588.
@article{b20076a8646945a69db1cc13ef69ea3c,
title = "10-bit 30-MS/s SAR ADC using a switchback switching method",
abstract = "This brief presents a 10-bit 30-MS/s successive-approximation-register analog-to-digital converter (ADC) that uses a power efficient switchback switching method. With respect to the monotonic switching method, the input common-mode voltage variation reduces which improves the dynamic offset and the parasitic capacitance variation of the comparator. The proposed switchback switching method does not consume any power at the first digital-to-analog converter switching, which can reduce the power consumption and design effort of the reference buffer. The prototype was fabricated in a 90-nm 1P9M CMOS technology. At 1-V supply and 30 MS/s, the ADC achieves an sequenced neighbor double reservation of 56.89 dB and consumes 0.98 mW, resulting in a figure-of-merit (FOM) of 57 fJ/conversion-step. The ADC core occupies an active area of only 190×,525 μm2.",
author = "Huang, {Guan Ying} and Chang, {Soon Jyh} and Liu, {Chun Cheng} and Lin, {Ying Zu}",
year = "2013",
month = "3",
day = "11",
doi = "10.1109/TVLSI.2012.2190117",
language = "English",
volume = "21",
pages = "584--588",
journal = "IEEE Transactions on Very Large Scale Integration (VLSI) Systems",
issn = "1063-8210",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "3",

}

10-bit 30-MS/s SAR ADC using a switchback switching method. / Huang, Guan Ying; Chang, Soon Jyh; Liu, Chun Cheng; Lin, Ying Zu.

In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 21, No. 3, 6172687, 11.03.2013, p. 584-588.

Research output: Contribution to journalArticle

TY - JOUR

T1 - 10-bit 30-MS/s SAR ADC using a switchback switching method

AU - Huang, Guan Ying

AU - Chang, Soon Jyh

AU - Liu, Chun Cheng

AU - Lin, Ying Zu

PY - 2013/3/11

Y1 - 2013/3/11

N2 - This brief presents a 10-bit 30-MS/s successive-approximation-register analog-to-digital converter (ADC) that uses a power efficient switchback switching method. With respect to the monotonic switching method, the input common-mode voltage variation reduces which improves the dynamic offset and the parasitic capacitance variation of the comparator. The proposed switchback switching method does not consume any power at the first digital-to-analog converter switching, which can reduce the power consumption and design effort of the reference buffer. The prototype was fabricated in a 90-nm 1P9M CMOS technology. At 1-V supply and 30 MS/s, the ADC achieves an sequenced neighbor double reservation of 56.89 dB and consumes 0.98 mW, resulting in a figure-of-merit (FOM) of 57 fJ/conversion-step. The ADC core occupies an active area of only 190×,525 μm2.

AB - This brief presents a 10-bit 30-MS/s successive-approximation-register analog-to-digital converter (ADC) that uses a power efficient switchback switching method. With respect to the monotonic switching method, the input common-mode voltage variation reduces which improves the dynamic offset and the parasitic capacitance variation of the comparator. The proposed switchback switching method does not consume any power at the first digital-to-analog converter switching, which can reduce the power consumption and design effort of the reference buffer. The prototype was fabricated in a 90-nm 1P9M CMOS technology. At 1-V supply and 30 MS/s, the ADC achieves an sequenced neighbor double reservation of 56.89 dB and consumes 0.98 mW, resulting in a figure-of-merit (FOM) of 57 fJ/conversion-step. The ADC core occupies an active area of only 190×,525 μm2.

UR - http://www.scopus.com/inward/record.url?scp=84874614952&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84874614952&partnerID=8YFLogxK

U2 - 10.1109/TVLSI.2012.2190117

DO - 10.1109/TVLSI.2012.2190117

M3 - Article

AN - SCOPUS:84874614952

VL - 21

SP - 584

EP - 588

JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

SN - 1063-8210

IS - 3

M1 - 6172687

ER -