3D-IC BISR for stacked memories using cross-die spares

Chun Chuan Chi, Yung Fa Chou, Ding Ming Kwai, Yu Ying Hsiao, Cheng Wen Wu, Yu Tsao Hsing, Li Ming Denq, Tsung Hsiang Lin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Citations (Scopus)

Abstract

3D ICs based on Through-Silicon-Vias (TSVs) enable the stacking of logic and memory dies to manufacture chips with higher performance, lower power, and smaller form factor. To improve the yield of the memory dies in 3D ICs, this paper proposes aBuilt-In Self-Repair (BISR) architecture which allows the sharing of spares between different layers of dies. The corresponding pre-bond (before the memory dies are bonded together) and post-bond (after the memory dies are bonded together) test flow is presented as well. In order to maximize the yield gain introduced by the cross-die spares, a die matching algorithm is proposed to determine which dies should be stacked together, so that the spare sharing can be most ef~cient. Experimental results show that the area overhead of the proposed BISR circuit is only 2.43%, which can be smaller if larger logic and memory dies are adopted, and the yield gain achieved by cross-die spare sharing can be up to 23%.

Original languageEnglish
Title of host publication2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers
DOIs
Publication statusPublished - 2012 Jul 25
Event2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Hsinchu, Taiwan
Duration: 2012 Apr 232012 Apr 25

Publication series

Name2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers

Other

Other2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012
CountryTaiwan
CityHsinchu
Period12-04-2312-04-25

Fingerprint

Data storage equipment
Repair
Silicon
Networks (circuits)

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

Cite this

Chi, C. C., Chou, Y. F., Kwai, D. M., Hsiao, Y. Y., Wu, C. W., Hsing, Y. T., ... Lin, T. H. (2012). 3D-IC BISR for stacked memories using cross-die spares. In 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers [6212621] (2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers). https://doi.org/10.1109/VLSI-DAT.2012.6212621
Chi, Chun Chuan ; Chou, Yung Fa ; Kwai, Ding Ming ; Hsiao, Yu Ying ; Wu, Cheng Wen ; Hsing, Yu Tsao ; Denq, Li Ming ; Lin, Tsung Hsiang. / 3D-IC BISR for stacked memories using cross-die spares. 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers. 2012. (2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers).
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abstract = "3D ICs based on Through-Silicon-Vias (TSVs) enable the stacking of logic and memory dies to manufacture chips with higher performance, lower power, and smaller form factor. To improve the yield of the memory dies in 3D ICs, this paper proposes aBuilt-In Self-Repair (BISR) architecture which allows the sharing of spares between different layers of dies. The corresponding pre-bond (before the memory dies are bonded together) and post-bond (after the memory dies are bonded together) test flow is presented as well. In order to maximize the yield gain introduced by the cross-die spares, a die matching algorithm is proposed to determine which dies should be stacked together, so that the spare sharing can be most ef~cient. Experimental results show that the area overhead of the proposed BISR circuit is only 2.43{\%}, which can be smaller if larger logic and memory dies are adopted, and the yield gain achieved by cross-die spare sharing can be up to 23{\%}.",
author = "Chi, {Chun Chuan} and Chou, {Yung Fa} and Kwai, {Ding Ming} and Hsiao, {Yu Ying} and Wu, {Cheng Wen} and Hsing, {Yu Tsao} and Denq, {Li Ming} and Lin, {Tsung Hsiang}",
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Chi, CC, Chou, YF, Kwai, DM, Hsiao, YY, Wu, CW, Hsing, YT, Denq, LM & Lin, TH 2012, 3D-IC BISR for stacked memories using cross-die spares. in 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers., 6212621, 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers, 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012, Hsinchu, Taiwan, 12-04-23. https://doi.org/10.1109/VLSI-DAT.2012.6212621

3D-IC BISR for stacked memories using cross-die spares. / Chi, Chun Chuan; Chou, Yung Fa; Kwai, Ding Ming; Hsiao, Yu Ying; Wu, Cheng Wen; Hsing, Yu Tsao; Denq, Li Ming; Lin, Tsung Hsiang.

2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers. 2012. 6212621 (2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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N2 - 3D ICs based on Through-Silicon-Vias (TSVs) enable the stacking of logic and memory dies to manufacture chips with higher performance, lower power, and smaller form factor. To improve the yield of the memory dies in 3D ICs, this paper proposes aBuilt-In Self-Repair (BISR) architecture which allows the sharing of spares between different layers of dies. The corresponding pre-bond (before the memory dies are bonded together) and post-bond (after the memory dies are bonded together) test flow is presented as well. In order to maximize the yield gain introduced by the cross-die spares, a die matching algorithm is proposed to determine which dies should be stacked together, so that the spare sharing can be most ef~cient. Experimental results show that the area overhead of the proposed BISR circuit is only 2.43%, which can be smaller if larger logic and memory dies are adopted, and the yield gain achieved by cross-die spare sharing can be up to 23%.

AB - 3D ICs based on Through-Silicon-Vias (TSVs) enable the stacking of logic and memory dies to manufacture chips with higher performance, lower power, and smaller form factor. To improve the yield of the memory dies in 3D ICs, this paper proposes aBuilt-In Self-Repair (BISR) architecture which allows the sharing of spares between different layers of dies. The corresponding pre-bond (before the memory dies are bonded together) and post-bond (after the memory dies are bonded together) test flow is presented as well. In order to maximize the yield gain introduced by the cross-die spares, a die matching algorithm is proposed to determine which dies should be stacked together, so that the spare sharing can be most ef~cient. Experimental results show that the area overhead of the proposed BISR circuit is only 2.43%, which can be smaller if larger logic and memory dies are adopted, and the yield gain achieved by cross-die spare sharing can be up to 23%.

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Chi CC, Chou YF, Kwai DM, Hsiao YY, Wu CW, Hsing YT et al. 3D-IC BISR for stacked memories using cross-die spares. In 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers. 2012. 6212621. (2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers). https://doi.org/10.1109/VLSI-DAT.2012.6212621