3D-IC interconnect test, diagnosis, and repair

Chun Chuan Chi, Cheng Wen Wu, Min Jer Wang, Hung Chih Lin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

35 Citations (Scopus)

Abstract

Through-Silicon-Via (TSV)-based three-dimensional ICs (3D-ICs) have gained increasing attention due to their potential in reducing manufacturing costs and capability of integrating more functionality into a single chip. One of the most important factors that affect 3D-IC yield is the integrity of interconnects which connect different dies in a 3D-IC. This paper proposes a Design-for-Test (DIT) scheme that can 1) detect faulty interconnects in 3D-ICs, 2) pinpoint open defect locations to help yield learning, and 3) repair faulty interconnects caused by open defects to improve the 3D-IC yield. Experimental results show that the proposed scheme can achieve a diagnosis resolution of 84% for open defects. With the interconnect repair mechanism, the 3D-IC yield is improved by 10%. In addition, cost-benefit analysis reveals that the proposed technique can significantly increase the net profit, especially when the natural interconnect yield is low.

Original languageEnglish
Title of host publicationProceedings - 2013 IEEE 31st VLSI Test Symposium, VTS 2013
DOIs
Publication statusPublished - 2013 Aug 14
Event2013 IEEE 31st VLSI Test Symposium, VTS 2013 - Berkeley, CA, United States
Duration: 2013 Apr 292013 May 1

Publication series

NameProceedings of the IEEE VLSI Test Symposium

Conference

Conference2013 IEEE 31st VLSI Test Symposium, VTS 2013
CountryUnited States
CityBerkeley, CA
Period13-04-2913-05-01

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Electrical and Electronic Engineering

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