3D-IC interconnect test, diagnosis, and repair

Chun Chuan Chi; Cheng Wen Wu; Min Jer Wang; Hung Chih Lin

doi:10.1109/VTS.2013.6548905

3D-IC interconnect test, diagnosis, and repair

Chun Chuan Chi
, Cheng Wen Wu
, Min Jer Wang
, Hung Chih Lin

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

50 Citations (Scopus)

Abstract

Through-Silicon-Via (TSV)-based three-dimensional ICs (3D-ICs) have gained increasing attention due to their potential in reducing manufacturing costs and capability of integrating more functionality into a single chip. One of the most important factors that affect 3D-IC yield is the integrity of interconnects which connect different dies in a 3D-IC. This paper proposes a Design-for-Test (DIT) scheme that can 1) detect faulty interconnects in 3D-ICs, 2) pinpoint open defect locations to help yield learning, and 3) repair faulty interconnects caused by open defects to improve the 3D-IC yield. Experimental results show that the proposed scheme can achieve a diagnosis resolution of 84% for open defects. With the interconnect repair mechanism, the 3D-IC yield is improved by 10%. In addition, cost-benefit analysis reveals that the proposed technique can significantly increase the net profit, especially when the natural interconnect yield is low.

Original language	English
Title of host publication	Proceedings - 2013 IEEE 31st VLSI Test Symposium, VTS 2013
DOIs	https://doi.org/10.1109/VTS.2013.6548905
Publication status	Published - 2013 Aug 14
Event	2013 IEEE 31st VLSI Test Symposium, VTS 2013 - Berkeley, CA, United States Duration: 2013 Apr 29 → 2013 May 1

Publication series

Name	Proceedings of the IEEE VLSI Test Symposium

Conference

Conference	2013 IEEE 31st VLSI Test Symposium, VTS 2013
Country/Territory	United States
City	Berkeley, CA
Period	13-04-29 → 13-05-01

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 9 Industry, Innovation, and Infrastructure

All Science Journal Classification (ASJC) codes

Computer Science Applications
Electrical and Electronic Engineering

Access to Document

10.1109/VTS.2013.6548905

Cite this

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title = "3D-IC interconnect test, diagnosis, and repair",

abstract = "Through-Silicon-Via (TSV)-based three-dimensional ICs (3D-ICs) have gained increasing attention due to their potential in reducing manufacturing costs and capability of integrating more functionality into a single chip. One of the most important factors that affect 3D-IC yield is the integrity of interconnects which connect different dies in a 3D-IC. This paper proposes a Design-for-Test (DIT) scheme that can 1) detect faulty interconnects in 3D-ICs, 2) pinpoint open defect locations to help yield learning, and 3) repair faulty interconnects caused by open defects to improve the 3D-IC yield. Experimental results show that the proposed scheme can achieve a diagnosis resolution of 84\% for open defects. With the interconnect repair mechanism, the 3D-IC yield is improved by 10\%. In addition, cost-benefit analysis reveals that the proposed technique can significantly increase the net profit, especially when the natural interconnect yield is low.",

author = "Chi, \{Chun Chuan\} and Wu, \{Cheng Wen\} and Wang, \{Min Jer\} and Lin, \{Hung Chih\}",

year = "2013",

month = aug,

day = "14",

doi = "10.1109/VTS.2013.6548905",

language = "English",

isbn = "9781467355438",

series = "Proceedings of the IEEE VLSI Test Symposium",

booktitle = "Proceedings - 2013 IEEE 31st VLSI Test Symposium, VTS 2013",

note = "2013 IEEE 31st VLSI Test Symposium, VTS 2013 ; Conference date: 29-04-2013 Through 01-05-2013",

}

TY - GEN

T1 - 3D-IC interconnect test, diagnosis, and repair

AU - Chi, Chun Chuan

AU - Wu, Cheng Wen

AU - Wang, Min Jer

AU - Lin, Hung Chih

PY - 2013/8/14

Y1 - 2013/8/14

N2 - Through-Silicon-Via (TSV)-based three-dimensional ICs (3D-ICs) have gained increasing attention due to their potential in reducing manufacturing costs and capability of integrating more functionality into a single chip. One of the most important factors that affect 3D-IC yield is the integrity of interconnects which connect different dies in a 3D-IC. This paper proposes a Design-for-Test (DIT) scheme that can 1) detect faulty interconnects in 3D-ICs, 2) pinpoint open defect locations to help yield learning, and 3) repair faulty interconnects caused by open defects to improve the 3D-IC yield. Experimental results show that the proposed scheme can achieve a diagnosis resolution of 84% for open defects. With the interconnect repair mechanism, the 3D-IC yield is improved by 10%. In addition, cost-benefit analysis reveals that the proposed technique can significantly increase the net profit, especially when the natural interconnect yield is low.

AB - Through-Silicon-Via (TSV)-based three-dimensional ICs (3D-ICs) have gained increasing attention due to their potential in reducing manufacturing costs and capability of integrating more functionality into a single chip. One of the most important factors that affect 3D-IC yield is the integrity of interconnects which connect different dies in a 3D-IC. This paper proposes a Design-for-Test (DIT) scheme that can 1) detect faulty interconnects in 3D-ICs, 2) pinpoint open defect locations to help yield learning, and 3) repair faulty interconnects caused by open defects to improve the 3D-IC yield. Experimental results show that the proposed scheme can achieve a diagnosis resolution of 84% for open defects. With the interconnect repair mechanism, the 3D-IC yield is improved by 10%. In addition, cost-benefit analysis reveals that the proposed technique can significantly increase the net profit, especially when the natural interconnect yield is low.

UR - https://www.scopus.com/pages/publications/84881290625

UR - https://www.scopus.com/pages/publications/84881290625#tab=citedBy

U2 - 10.1109/VTS.2013.6548905

DO - 10.1109/VTS.2013.6548905

M3 - Conference contribution

AN - SCOPUS:84881290625

SN - 9781467355438

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BT - Proceedings - 2013 IEEE 31st VLSI Test Symposium, VTS 2013

T2 - 2013 IEEE 31st VLSI Test Symposium, VTS 2013

Y2 - 29 April 2013 through 1 May 2013

ER -

3D-IC interconnect test, diagnosis, and repair

Abstract

Publication series

Conference

UN SDGs

All Science Journal Classification (ASJC) codes

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