3D-IC test architecture for TSVs with different impact ranges of crosstalk faults

Wen Hsuan Hsu, Michael A. Kochte, Kuen Jong Lee

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

Through Silicon Vias (TSV) play an important role in 3D chip integration. Its features include: providing vertical interconnection, decreasing the area of routing, and increasing the bandwidth. Effective and efficient testing for correct operation of TSVs is an essential issue for 3D ICs. This work focuses on crosstalk faults with different impact ranges and proposes a TSV grouping method to test as many TSVs simultaneously as possible. Based on the results of the TSV grouping, we also implement a high-efficiency, low-area-overhead TSV test architecture.

Original languageEnglish
Title of host publication2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781467394987
DOIs
Publication statusPublished - 2016 May 31
Event2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016 - Hsinchu, Taiwan
Duration: 2016 Apr 252016 Apr 27

Publication series

Name2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016

Other

Other2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016
CountryTaiwan
CityHsinchu
Period16-04-2516-04-27

Fingerprint

Crosstalk
crosstalk
Silicon
silicon
chips
bandwidth
Bandwidth
Testing

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality
  • Instrumentation

Cite this

Hsu, W. H., Kochte, M. A., & Lee, K. J. (2016). 3D-IC test architecture for TSVs with different impact ranges of crosstalk faults. In 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016 [7482554] (2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-DAT.2016.7482554
Hsu, Wen Hsuan ; Kochte, Michael A. ; Lee, Kuen Jong. / 3D-IC test architecture for TSVs with different impact ranges of crosstalk faults. 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016. Institute of Electrical and Electronics Engineers Inc., 2016. (2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016).
@inproceedings{8104879302bd4059a84f04fea5f1de33,
title = "3D-IC test architecture for TSVs with different impact ranges of crosstalk faults",
abstract = "Through Silicon Vias (TSV) play an important role in 3D chip integration. Its features include: providing vertical interconnection, decreasing the area of routing, and increasing the bandwidth. Effective and efficient testing for correct operation of TSVs is an essential issue for 3D ICs. This work focuses on crosstalk faults with different impact ranges and proposes a TSV grouping method to test as many TSVs simultaneously as possible. Based on the results of the TSV grouping, we also implement a high-efficiency, low-area-overhead TSV test architecture.",
author = "Hsu, {Wen Hsuan} and Kochte, {Michael A.} and Lee, {Kuen Jong}",
year = "2016",
month = "5",
day = "31",
doi = "10.1109/VLSI-DAT.2016.7482554",
language = "English",
series = "2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016",
address = "United States",

}

Hsu, WH, Kochte, MA & Lee, KJ 2016, 3D-IC test architecture for TSVs with different impact ranges of crosstalk faults. in 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016., 7482554, 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016, Institute of Electrical and Electronics Engineers Inc., 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016, Hsinchu, Taiwan, 16-04-25. https://doi.org/10.1109/VLSI-DAT.2016.7482554

3D-IC test architecture for TSVs with different impact ranges of crosstalk faults. / Hsu, Wen Hsuan; Kochte, Michael A.; Lee, Kuen Jong.

2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016. Institute of Electrical and Electronics Engineers Inc., 2016. 7482554 (2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - 3D-IC test architecture for TSVs with different impact ranges of crosstalk faults

AU - Hsu, Wen Hsuan

AU - Kochte, Michael A.

AU - Lee, Kuen Jong

PY - 2016/5/31

Y1 - 2016/5/31

N2 - Through Silicon Vias (TSV) play an important role in 3D chip integration. Its features include: providing vertical interconnection, decreasing the area of routing, and increasing the bandwidth. Effective and efficient testing for correct operation of TSVs is an essential issue for 3D ICs. This work focuses on crosstalk faults with different impact ranges and proposes a TSV grouping method to test as many TSVs simultaneously as possible. Based on the results of the TSV grouping, we also implement a high-efficiency, low-area-overhead TSV test architecture.

AB - Through Silicon Vias (TSV) play an important role in 3D chip integration. Its features include: providing vertical interconnection, decreasing the area of routing, and increasing the bandwidth. Effective and efficient testing for correct operation of TSVs is an essential issue for 3D ICs. This work focuses on crosstalk faults with different impact ranges and proposes a TSV grouping method to test as many TSVs simultaneously as possible. Based on the results of the TSV grouping, we also implement a high-efficiency, low-area-overhead TSV test architecture.

UR - http://www.scopus.com/inward/record.url?scp=84978410085&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84978410085&partnerID=8YFLogxK

U2 - 10.1109/VLSI-DAT.2016.7482554

DO - 10.1109/VLSI-DAT.2016.7482554

M3 - Conference contribution

AN - SCOPUS:84978410085

T3 - 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016

BT - 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016

PB - Institute of Electrical and Electronics Engineers Inc.

ER -

Hsu WH, Kochte MA, Lee KJ. 3D-IC test architecture for TSVs with different impact ranges of crosstalk faults. In 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016. Institute of Electrical and Electronics Engineers Inc. 2016. 7482554. (2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016). https://doi.org/10.1109/VLSI-DAT.2016.7482554