3D-IC test architecture for TSVs with different impact ranges of crosstalk faults

Wen Hsuan Hsu; Michael A. Kochte; Kuen Jong Lee

doi:10.1109/VLSI-DAT.2016.7482554

3D-IC test architecture for TSVs with different impact ranges of crosstalk faults

Wen Hsuan Hsu, Michael A. Kochte, Kuen Jong Lee

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

Through Silicon Vias (TSV) play an important role in 3D chip integration. Its features include: providing vertical interconnection, decreasing the area of routing, and increasing the bandwidth. Effective and efficient testing for correct operation of TSVs is an essential issue for 3D ICs. This work focuses on crosstalk faults with different impact ranges and proposes a TSV grouping method to test as many TSVs simultaneously as possible. Based on the results of the TSV grouping, we also implement a high-efficiency, low-area-overhead TSV test architecture.

Original language	English
Title of host publication	2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781467394987
DOIs	https://doi.org/10.1109/VLSI-DAT.2016.7482554
Publication status	Published - 2016 May 31
Event	2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016 - Hsinchu, Taiwan Duration: 2016 Apr 25 → 2016 Apr 27

Publication series

Name	2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016

Other

Other	2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016
Country/Territory	Taiwan
City	Hsinchu
Period	16-04-25 → 16-04-27

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering
Safety, Risk, Reliability and Quality
Instrumentation

Access to Document

10.1109/VLSI-DAT.2016.7482554

Cite this

Hsu, W. H., Kochte, M. A., & Lee, K. J. (2016). 3D-IC test architecture for TSVs with different impact ranges of crosstalk faults. In 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016 [7482554] (2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-DAT.2016.7482554

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title = "3D-IC test architecture for TSVs with different impact ranges of crosstalk faults",

abstract = "Through Silicon Vias (TSV) play an important role in 3D chip integration. Its features include: providing vertical interconnection, decreasing the area of routing, and increasing the bandwidth. Effective and efficient testing for correct operation of TSVs is an essential issue for 3D ICs. This work focuses on crosstalk faults with different impact ranges and proposes a TSV grouping method to test as many TSVs simultaneously as possible. Based on the results of the TSV grouping, we also implement a high-efficiency, low-area-overhead TSV test architecture.",

author = "Hsu, {Wen Hsuan} and Kochte, {Michael A.} and Lee, {Kuen Jong}",

note = "Funding Information: This work was partially supported by the Ministry of Science and Technology of Taiwan under contract 104-2811-E-006 -036 and 102- 2221-E-006-270- MY3. Publisher Copyright: {\textcopyright} 2016 IEEE.; 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016 ; Conference date: 25-04-2016 Through 27-04-2016",

year = "2016",

month = may,

day = "31",

doi = "10.1109/VLSI-DAT.2016.7482554",

language = "English",

series = "2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016",

address = "United States",

}

Hsu, WH, Kochte, MA & Lee, KJ 2016, 3D-IC test architecture for TSVs with different impact ranges of crosstalk faults. in 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016., 7482554, 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016, Institute of Electrical and Electronics Engineers Inc., 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016, Hsinchu, Taiwan, 16-04-25. https://doi.org/10.1109/VLSI-DAT.2016.7482554

3D-IC test architecture for TSVs with different impact ranges of crosstalk faults. / Hsu, Wen Hsuan; Kochte, Michael A.; Lee, Kuen Jong.

2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016. Institute of Electrical and Electronics Engineers Inc., 2016. 7482554 (2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - 3D-IC test architecture for TSVs with different impact ranges of crosstalk faults

AU - Hsu, Wen Hsuan

AU - Kochte, Michael A.

AU - Lee, Kuen Jong

N1 - Funding Information: This work was partially supported by the Ministry of Science and Technology of Taiwan under contract 104-2811-E-006 -036 and 102- 2221-E-006-270- MY3. Publisher Copyright: © 2016 IEEE.

PY - 2016/5/31

Y1 - 2016/5/31

N2 - Through Silicon Vias (TSV) play an important role in 3D chip integration. Its features include: providing vertical interconnection, decreasing the area of routing, and increasing the bandwidth. Effective and efficient testing for correct operation of TSVs is an essential issue for 3D ICs. This work focuses on crosstalk faults with different impact ranges and proposes a TSV grouping method to test as many TSVs simultaneously as possible. Based on the results of the TSV grouping, we also implement a high-efficiency, low-area-overhead TSV test architecture.

AB - Through Silicon Vias (TSV) play an important role in 3D chip integration. Its features include: providing vertical interconnection, decreasing the area of routing, and increasing the bandwidth. Effective and efficient testing for correct operation of TSVs is an essential issue for 3D ICs. This work focuses on crosstalk faults with different impact ranges and proposes a TSV grouping method to test as many TSVs simultaneously as possible. Based on the results of the TSV grouping, we also implement a high-efficiency, low-area-overhead TSV test architecture.

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M3 - Conference contribution

AN - SCOPUS:84978410085

T3 - 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016

BT - 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016

Y2 - 25 April 2016 through 27 April 2016

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Hsu WH, Kochte MA, Lee KJ. 3D-IC test architecture for TSVs with different impact ranges of crosstalk faults. In 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016. Institute of Electrical and Electronics Engineers Inc. 2016. 7482554. (2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016). doi: 10.1109/VLSI-DAT.2016.7482554

3D-IC test architecture for TSVs with different impact ranges of crosstalk faults

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