50 nm vertical surround gate MOSFET with S-factor of 75mV/dec

R. Li; Y. Zhang; Y. Lu; Sung Choi Daniel Sung Choi; M. Luo; K. L. Wang

50 nm vertical surround gate MOSFET with S-factor of 75mV/dec

R. Li, Y. Zhang, Y. Lu, Sung Choi Daniel Sung Choi, M. Luo, K. L. Wang

College of Electrical Engineering and Computer Science

Research output: Contribution to conference › Paper › peer-review

4 Citations (Scopus)

Abstract

Fully depleted vertical metal oxide semiconductor field effect transistors (MOSFET) were fabricated, characterized. A self-aligned process was used to fabricate the structure on silicon walls. The vertical MOSFET exposed by focus ion microbeam milling was analyzed by scanning electron microscopy.

Original language	English
Pages	63-64
Number of pages	2
Publication status	Published - 2001
Event	Device Research Conference (DRC) - Notre Dame, IN, United States Duration: 2001 Jun 25 → 2001 Jun 27

Conference

Conference	Device Research Conference (DRC)
Country/Territory	United States
City	Notre Dame, IN
Period	01-06-25 → 01-06-27

All Science Journal Classification (ASJC) codes

General Engineering

Cite this

@conference{6ccd98205d494890b51fbbe21d1b2dc0,

title = "50 nm vertical surround gate MOSFET with S-factor of 75mV/dec",

abstract = "Fully depleted vertical metal oxide semiconductor field effect transistors (MOSFET) were fabricated, characterized. A self-aligned process was used to fabricate the structure on silicon walls. The vertical MOSFET exposed by focus ion microbeam milling was analyzed by scanning electron microscopy.",

author = "R. Li and Y. Zhang and Y. Lu and {Daniel Sung Choi}, {Sung Choi} and M. Luo and Wang, {K. L.}",

year = "2001",

language = "English",

pages = "63--64",

}

TY - CONF

T1 - 50 nm vertical surround gate MOSFET with S-factor of 75mV/dec

AU - Li, R.

AU - Zhang, Y.

AU - Lu, Y.

AU - Daniel Sung Choi, Sung Choi

AU - Luo, M.

AU - Wang, K. L.

PY - 2001

Y1 - 2001

N2 - Fully depleted vertical metal oxide semiconductor field effect transistors (MOSFET) were fabricated, characterized. A self-aligned process was used to fabricate the structure on silicon walls. The vertical MOSFET exposed by focus ion microbeam milling was analyzed by scanning electron microscopy.

AB - Fully depleted vertical metal oxide semiconductor field effect transistors (MOSFET) were fabricated, characterized. A self-aligned process was used to fabricate the structure on silicon walls. The vertical MOSFET exposed by focus ion microbeam milling was analyzed by scanning electron microscopy.

UR - http://www.scopus.com/inward/record.url?scp=0034860406&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0034860406&partnerID=8YFLogxK

M3 - Paper

AN - SCOPUS:0034860406

SP - 63

EP - 64

T2 - Device Research Conference (DRC)

Y2 - 25 June 2001 through 27 June 2001

ER -

50 nm vertical surround gate MOSFET with S-factor of 75mV/dec

Abstract

Conference

All Science Journal Classification (ASJC) codes

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