6-T SRAM cell design with gate-all-around silicon nanowire MOSFETs

Yi Bo Liao, Meng Hsueh Chiang, Nattapol Damrongplasit, Tsu Jae King Liu, Wei Chou Hsu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Abstract

6T-SRAM cell design with gate-all-around (GAA) silicon nanowire (NW) MOSFETs is investigated via three-dimensional TCAD simulations and compact analytical modeling. A rectangular NW channel design allows the transistor width to be adjusted with reduced impact on short-channel effects. This in turn provides a means for tuning the cell ratios to optimize the tradeoff between static noise margin and writeability with optimal cell layout area efficiency.

Original languageEnglish
Title of host publication2013 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2013
DOIs
Publication statusPublished - 2013 Aug 12
Event2013 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2013 - Hsinchu, Taiwan
Duration: 2013 Apr 222013 Apr 24

Publication series

Name2013 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2013

Other

Other2013 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2013
CountryTaiwan
CityHsinchu
Period13-04-2213-04-24

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All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Liao, Y. B., Chiang, M. H., Damrongplasit, N., Liu, T. J. K., & Hsu, W. C. (2013). 6-T SRAM cell design with gate-all-around silicon nanowire MOSFETs. In 2013 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2013 [6545631] (2013 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2013). https://doi.org/10.1109/VLSI-TSA.2013.6545631