6-T SRAM performance assessment with stacked silicon nanowire MOSFETs

Ya Chi Huang, Meng-Hsueh Chiang, Wei-Chou Hsu, Shiou Ying Cheng

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

This paper assesses the 6-T SRAM performance and provides the design methodology with stacked gate-all-around silicon nanowire (NW) MOSFETs. To achieve high density design while preserving performance, different numbers of stacked NW MOSFETs are investigated via three-dimensional TCAD simulation. Due to tradeoff between read stability and writeability margins, adjusting the relative strengths of the transistors is needed but it can not be done straightforwardly as the widths of transistors are now quantized. Furthermore, when 3D stacking nanowires technique is used, another design issue with various stacked transistors has to be taken into account. This work simulates butterfly curves and N-curves to assess the device performance and provides an optimal design methodology for feasible manufacturability and good performance while using high density stacking technique. It is suggested that for the same stacked layers, though high stacking number favors writeability, it is limited to three layers due to source/drain series resistances. The double stacking is feasible for balanced read and write performances.

Original languageEnglish
Title of host publicationProceedings of the 16th International Symposium on Quality Electronic Design, ISQED 2015
PublisherIEEE Computer Society
Pages610-614
Number of pages5
ISBN (Electronic)9781479975815
DOIs
Publication statusPublished - 2015 Apr 13
Event16th International Symposium on Quality Electronic Design, ISQED 2015 - Santa Clara, United States
Duration: 2015 Mar 22015 Mar 4

Publication series

NameProceedings - International Symposium on Quality Electronic Design, ISQED
Volume2015-April
ISSN (Print)1948-3287
ISSN (Electronic)1948-3295

Other

Other16th International Symposium on Quality Electronic Design, ISQED 2015
CountryUnited States
CitySanta Clara
Period15-03-0215-03-04

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

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