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  • Cheng-Wen Wu
2019

A Self-Organizing Map-Based Adaptive Traffic Light Control System with Reinforcement Learning

Kao, Y. C. & Wu, C. W., 2019 Feb 19, Conference Record of the 52nd Asilomar Conference on Signals, Systems and Computers, ACSSC 2018. Matthews, M. B. (ed.). IEEE Computer Society, p. 2060-2064 5 p. 8645125. (Conference Record - Asilomar Conference on Signals, Systems and Computers; vol. 2018-October).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Redio: Accelerating Disk-Based Graph Processing by Reducing Disk I/Os

Wu, C., Zhang, G., Wang, Y., Jiang, X. & Zheng, W., 2019 Mar 1, In : IEEE Transactions on Computers. 68, 3, p. 414-425 12 p., 8489961.

Research output: Contribution to journalArticle

Solutions to Multiple Probing Challenges for Test Access to Multi-Die Stacked Integrated Circuits

Marinissen, E. J., Fodor, F., Podpod, A., Stucchi, M., Jian, Y. R. & Wu, C. W., 2019 Jan 23, International Test Conference 2018, ITC 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 8624731. (Proceedings - International Test Conference; vol. 2018-October).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

The last byte: Baseball and testing

Wu, C. W., 2019 Dec, In : IEEE Design and Test. 36, 6, 1 p., 8844727.

Research output: Contribution to journalComment/debate

2018

A Built-in Self-Test Scheme for Detecting Defects in FinFET-Based SRAM Circuit

Chen, M. C., Wu, T. H. & Wu, C. W., 2018 Dec 6, Proceedings - 2018 IEEE 27th Asian Test Symposium, ATS 2018. IEEE Computer Society, p. 19-24 6 p. 8567404. (Proceedings of the Asian Test Symposium; vol. 2018-October).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A Deep Learning-Based Screening Method for Improving the Quality and Reliability of Integrated Passive Devices

Pan, Y-C., Jian, Y-R., Liu, H-H. & Wu, C-W., 2018 Jul, VLSI Test Technology Workshop (VTTW). Nantou

Research output: Chapter in Book/Report/Conference proceedingConference contribution

An enhanced boundary scan architecture for inter-die interconnect leakage measurement in 2.5D and 3D packages

Law, P. M. P., Wu, C. W., Lin, L. Y. & Hong, H. C., 2018 Jan 24, Proceedings - 2017 IEEE 26th Asian Test Symposium, ATS 2017. Taipei: IEEE Computer Society, p. 1-6 6 p. (Proceedings of the Asian Test Symposium).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Automated Probe-Mark Analysis

Wu, C-W., Jian, Y-R., Fodor, F. & Marinissen, E. J., 2018 Jun, Semiconductor Wafer Test Workshop (SWTW).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Covering hard-To-detect defects by thermal quorum sensing

Chuang, P. Y., Wu, C. W. & Chen, H. H., 2018 Jun 29, Proceedings - 2018 23rd IEEE European Test Symposium, ETS 2018. Bremen: Institute of Electrical and Electronics Engineers Inc., p. 1-2 2 p. (Proceedings of the European Test Workshop; vol. 2018-May).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

RRAM-based neuromorphic hardware reliability improvement by self-healing and error correction

Hu, J. Y., Hou, K. W., Lo, C. Y., Chou, Y. F. & Wu, C. W., 2018 Sep 11, Proceedings - 2nd IEEE International Test Conference in Asia, ITC-Asia 2018. Institute of Electrical and Electronics Engineers Inc., p. 19-24 6 p. 8462942. (Proceedings - 2nd IEEE International Test Conference in Asia, ITC-Asia 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Symbiotic Controller Design Using a Memory-Based FSM Model

Kuo, S. F. & Wu, C. W., 2018 Aug 10, Proceedings - 2018 IEEE 27th International Symposium on Industrial Electronics, ISIE 2018. Institute of Electrical and Electronics Engineers Inc., p. 874-879 6 p. 8433783. (IEEE International Symposium on Industrial Electronics; vol. 2018-June).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2017

A Built-Off Self-Repair Scheme for Channel-Based 3D Memories

Liu, H. H., Lin, B. Y., Wu, C. W., Chiang, W. T., Mincent, L., Lin, H. C., Peng, C. N. & Wang, M. J., 2017 Aug 1, In : IEEE Transactions on Computers. 66, 8, p. 1293-1301 9 p., 7850958.

Research output: Contribution to journalArticle

2 Citations (Scopus)

Building a fault tolerant framework with deadline guarantee in big data stream computing environments

Sun, D., Zhang, G., Wu, C., Li, K. & Zheng, W., 2017 Nov, In : Journal of Computer and System Sciences. 89, p. 4-23 20 p.

Research output: Contribution to journalArticle

11 Citations (Scopus)

Cell-Aware Test Generation Time Reduction by Using Switch-Level ATPG

Wu, C-W., Chuang, P-Y. & Chen, H. H., 2017 Sep, IEEE Int. Test Conf. in Asia (ITC-A). Taipei

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Controller architecture for low-power, low-latency DRAM with built-in cache

Liu, Z. Y., Shih, H. C., Lin, B. Y. & Wu, C. W., 2017 Apr 1, In : IEEE Design and Test. 34, 2, p. 69-78 10 p., 7397924.

Research output: Contribution to journalArticle

1 Citation (Scopus)

Fault Models and Test Algorithms for Multi-Level Cell (MLC) Crossbar RRAM

Wu, C-W. & Hou, K-W., 2017 Jul, VLSI Test Technology Workshop (VTTW). Nantou

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Foreword

Wu, C. W., Lee, K. J., Wang, L. C. & Huang, S. Y., 2017 Nov 3, In : ITC-Asia 2017 - International Test Conference in Asia. p. iv 8097094.

Research output: Contribution to journalEditorial

Highly Reliable and Low-Cost Symbiotic IOT Devices and Systems

Wu, C-W., Lin, B-Y., Hung, H-W., Tseng, S-M. & Chen, C., 2017 Oct, IEEE Int. Test Conf. (ITC). Fort Worth, Texas

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Large graph computing systems

Wu, C., Zhang, G., Li, K. & Zheng, W., 2017 Jan 1, Big Data Management and Processing. CRC Press, p. 347-362 16 p.

Research output: Chapter in Book/Report/Conference proceedingChapter

Symbiotic system models for efficient IGT system design and test

Wu, C. W., Lin, B. Y., Hung, H. W., Tseng, S. M. & Chen, C., 2017 Nov 3, ITC-Asia 2017 - International Test Conference in Asia. Institute of Electrical and Electronics Engineers Inc., p. 71-76 6 p. 8097114. (ITC-Asia 2017 - International Test Conference in Asia).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Symbiotic System Models for Efficient IOT System Design and Test

Wu, C-W., Chen, C., Lin, B-Y., Hung, H-W. & Tseng, S-M., 2017 Sep, IEEE Int. Test Conf. in Asia (ITC-A). Taipei

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Test Cost Reduction Methodology for InFO Wafer-Level Chip-Scale Package

Wang, K. L., Lin, B. Y., Wu, C. W., Lee, M., Chen, H., Lin, H. C., Peng, C. N. & Wang, M. J., 2017 Jun 1, In : IEEE Design and Test. 34, 3, p. 50-58 9 p., 7464303.

Research output: Contribution to journalArticle

3 Citations (Scopus)
2016

A fast sweep-line-based failure pattern extractor for memory diagnosis

Wei, S. Y., Lin, B. Y. & Wu, C. W., 2016 Jul 22, Proceedings - 2016 21st IEEE European Test Symposium, ETS 2016. Institute of Electrical and Electronics Engineers Inc., 7519314. (Proceedings of the European Test Workshop; vol. 2016-July).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

A local parallel search approach for memory failure pattern identification

Lin, B. Y., Wu, C. W., Lee, M., Lin, H. C., Peng, C. N. & Wang, M. J., 2016 Mar 1, In : IEEE Transactions on Computers. 65, 3, p. 770-780 11 p., 7173026.

Research output: Contribution to journalArticle

3 Citations (Scopus)

Configurable Cubical Redundancy Schemes for Channel-Based 3-D DRAM Yield Improvement

Lin, B. Y., Chiang, W. T., Wu, C. W., Lee, M., Lin, H. C., Peng, C. N. & Wang, M. J., 2016 Apr 1, In : IEEE Design and Test. 33, 2, p. 30-39 10 p., 7154435.

Research output: Contribution to journalArticle

1 Citation (Scopus)

Efficient Cell-Aware Fault Modeling by Switch-Level Test Generation

Chen, H. H., Chen, S. Y. H., Chuang, P. Y. & Wu, C. W., 2016 Dec 22, Proceedings - 2016 IEEE 25th Asian Test Symposium, ATS 2016. IEEE Computer Society, p. 197-202 6 p. 7796112. (Proceedings of the Asian Test Symposium).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Efficient probing schemes for fine-pitch pads of InFO wafer-level chip-scale package

Huang, Y. C., Lin, B. Y., Wu, C. W., Lee, M., Chen, H., Lin, H. C., Peng, C. N. & Wang, M. J., 2016 Jun 5, Proceedings of the 53rd Annual Design Automation Conference, DAC 2016. Institute of Electrical and Electronics Engineers Inc., a58. (Proceedings - Design Automation Conference; vol. 05-09-June-2016).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Layout-Oriented Defect Set Reduction for Fast Circuit Simulation in Cell-Aware Test

Liu, H. W., Lin, B. Y. & Wu, C. W., 2016 Dec 22, Proceedings - 2016 IEEE 25th Asian Test Symposium, ATS 2016. IEEE Computer Society, p. 156-160 5 p. 7796105. (Proceedings of the Asian Test Symposium).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Rethinking computer architectures and software systems for phase-change memory

Wu, C., Zhang, G. & Li, K., 2016 May, In : ACM Journal on Emerging Technologies in Computing Systems. 12, 4, 33.

Research output: Contribution to journalArticle

5 Citations (Scopus)

Symbiotic-System Approach for IOT Devices

Wu, C-W., 2016 Nov, 25th IEEE Asian Test Symp. (ATS), Hiroshima. Hiroshima

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2015

A Computer Designed Half Gb 16-Channel 819Gb/s High-Bandwidth and 10ns Low-Latency DRAM for 3D Stacked Memory Devices Using TSVs

Wu, C-W., Luo, P-W., Chen, C-K., Sung, Y-H., Wu, W., Shih, H-C., Lee, C-H., Lee, K-H., Li, M-W., Lung, M-C., Lu, C-N., Chou, Y-F., Shih, P-L., Ke, C-H., Shiah, C., Stolt, P., Tomishima, S., Kwai, D-M., Rong, B-D., Lu, N. & 1 others, Lu, S-L., 2015 Jun, IEEE Symp. VLSI Circuits (VLSI).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Redundancy architectures for channel-based 3D DRAM yield improvement

Lin, B. Y., Chiang, W. T., Wu, C. W., Lee, M., Lin, H. C., Peng, C. N. & Wang, M. J., 2015 Feb 6, Proceedings - 2014 IEEE International Test Conference, ITC 2014. Seattle, Washington: Institute of Electrical and Electronics Engineers Inc., 7035331. (Proceedings - International Test Conference; vol. 2015-February).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

RRAM defect modeling and failure analysis based on march test and a novel squeeze-search scheme

Chen, C. Y., Shih, H. C., Wu, C. W., Lin, C. H., Chiu, P. F., Sheu, S. S. & Chen, F. T., 2015 Jan 1, In : IEEE Transactions on Computers. 64, 1, p. 180-190 11 p., 6725492.

Research output: Contribution to journalArticle

56 Citations (Scopus)

System-level test coverage prediction by structural stress test data mining

Lin, B. Y., Wu, C. W. & Chen, H. H., 2015 May 28, 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015. Institute of Electrical and Electronics Engineers Inc., 7114508. (2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2014

Application-independent testing of 3-D field programmable gate array interconnect faults

Peng, Y. L., Kwai, D. M., Chou, Y. F. & Wu, C. W., 2014 Feb 1, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 22, 2, p. 207-219 13 p., 6459051.

Research output: Contribution to journalArticle

5 Citations (Scopus)

BIST-assisted tuning scheme for minimizing io-channel power of TSV-based 3D DRAMs

Yu, Y. C., Yang, C. C., Li, J. F., Lo, C. Y., Chen, C. H., Lai, J. S., Kwai, D. M., Chou, Y. F. & Wu, C. W., 2014 Dec 7, Proceedings - 23rd Asian Test Symposium, ATS 2014. Hsinchu: IEEE Computer Society, p. 1-6 6 p. 06979068. (Proceedings of the Asian Test Symposium).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

DArT: A component-based DRAM area, power, and timing modeling tool

Shih, H. C., Luo, P. W., Yeh, J. C., Lin, S. Y., Kwai, D. M., Lu, S. L., Schaefer, A. & Wu, C. W., 2014 Jan 1, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 33, 9, p. 1356-1369 14 p., 6879579.

Research output: Contribution to journalArticle

11 Citations (Scopus)

DRAM system simulation speed-Up by effective-cycle selection

Chiang, H. C., Wang, M. Y. & Wu, C. W., 2014 Jan 1, Proceedings - 2014 International Symposium on Computer, Consumer and Control, IS3C 2014. IEEE Computer Society, p. 1053-1056 4 p. 6846067. (Proceedings - 2014 International Symposium on Computer, Consumer and Control, IS3C 2014).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Low-cost post-bond testing of 3-D ICs containing a passive silicon interposer base

Chi, C. C., Marinissen, E. J., Goel, S. K. & Wu, C. W., 2014 Nov 1, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 22, 11, p. 2388-2401 14 p., 6680768.

Research output: Contribution to journalArticle

6 Citations (Scopus)

On improving interconnect defect diagnosis resolution and yield for interposer-based 3-D ICs

Chi, C. C., Lin, B. Y., Wu, C. W., Wang, M. J., Lin, H. C. & Peng, C. N., 2014 Jan 1, In : IEEE Design and Test. 31, 4, p. 16-26 11 p., 6221038.

Research output: Contribution to journalArticle

5 Citations (Scopus)
2013

3D-IC interconnect test, diagnosis, and repair

Chi, C. C., Wu, C. W., Wang, M. J. & Lin, H. C., 2013 Aug 14, Proceedings - 2013 IEEE 31st VLSI Test Symposium, VTS 2013. 6548905. (Proceedings of the IEEE VLSI Test Symposium).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

34 Citations (Scopus)

A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS

Lin, T. J., Chien, C. A., Chang, P. Y., Chen, C. W., Wang, P. H., Shyu, T. Y., Chou, C. Y., Luo, S. C., Guo, J. I., Chen, T. F., Chuang, G. C. H., Chu, Y. H., Cheng, L. C., Su, H. M., Jou, C., Ieong, M., Wu, C. W. & Wang, J. S., 2013 Apr 29, 2013 IEEE International Solid-State Circuits Conference, ISSCC 2013 - Digest of Technical Papers. p. 158-159 2 p. 6487680. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; vol. 56).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

19 Citations (Scopus)

AC-plus scan methodology for small delay testing and characterization

Li, T. Y., Huang, S. Y., Hsu, H. J., Tzeng, C. W., Huang, C. T., Liou, J. J., Ma, H. P., Huang, P. C., Bor, J. C., Tien, C. C., Wang, C. H. & Wu, C. W., 2013 Jan 1, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 21, 2, p. 329-341 13 p., 6166352.

Research output: Contribution to journalArticle

2 Citations (Scopus)

A hybrid ECC and redundancy technique for reducing refresh power of DRAMs

Yu, Y. C., Hou, C. S., Chang, L. J., Li, J. F., Lo, C. Y., Kwai, D. M., Chou, Y. F. & Wu, C. W., 2013 Aug 14, Proceedings - 2013 IEEE 31st VLSI Test Symposium, VTS 2013. 6548927. (Proceedings of the IEEE VLSI Test Symposium).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Analytical modeling and numerical simulations of temperature field in TSV-based 3D ICs

Shiyanovskii, Y., Papachristou, C. & Wu, C. W., 2013 Jul 5, Proceedings of the 14th International Symposium on Quality Electronic Design, ISQED 2013. p. 24-29 6 p. 6523585. (Proceedings - International Symposium on Quality Electronic Design, ISQED).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

An enhanced double-TSV Scheme for defect tolerance in 3D-IC

Shih, H. C. & Wu, C. W., 2013 Oct 21, Proceedings - Design, Automation and Test in Europe, DATE 2013. p. 1486-1489 4 p. 6513748. (Proceedings -Design, Automation and Test in Europe, DATE).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

An FPGA-based test platform for analyzing data retention time distribution of DRAMs

Hou, C. S., Li, J. F., Lo, C. Y., Kwai, D. M., Chou, Y. F. & Wu, C. W., 2013 Aug 15, 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013. 6533853. (2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Citations (Scopus)

Exploration methodology for 3D memory redundancy architectures under redundancy constraints

Lin, B. Y., Lee, M. & Wu, C. W., 2013 Jan 1, In : Proceedings of the Asian Test Symposium. p. 1-6 6 p., 6690605.

Research output: Contribution to journalConference article

6 Citations (Scopus)

Exploration Methodology for 3D Memory Redun- dancy Architectures under Redundancy Constraints

Wu, C-W., Lin, B-Y. & Lee, M., 2013 Nov, 22nd IEEE Asian Test Symp. (ATS). Yilan

Research output: Chapter in Book/Report/Conference proceedingConference contribution