A 0.07-mm2162-mW DAC Achieving >65 dBc SFDR and < -70 dBc IM3 at 10 GS/s with Output Impedance Compensation and Concentric Parallelogram Routing

Hung Yi Huang, Tai Haur Kuo

Research output: Contribution to journalArticle

Abstract

A digital-to-analog converter (DAC) with small-size non-cascoded current cells is proposed to achieve small area, low-power consumption, and high linearity over a wide bandwidth. An output impedance compensation (OIC) technique using a compensation resistor, implemented by a PMOS with code-dependent gate voltage control, is proposed to remedy the nonlinearity induced by the insufficient output impedance of the non-cascoded current cells. In addition, a proposed concentric parallelogram routing (CPR) technique, in which the subcells of each current cell are arranged such that they form a parallelogram shape with a common centroid, is used to reduce both the mismatch error and the routing-induced timing skew among the current cells. The DAC, implemented in a 28-nm CMOS process, achieves >65-dBc spurious-free dynamic range (SFDR) and < -70-dBc third-order intermodulation distortion (IM3) over the entire Nyquist bandwidth at 10 GS/s while consuming 162 mW from a single 1.1 V supply.

Original languageEnglish
Article number9098055
Pages (from-to)2478-2488
Number of pages11
JournalIEEE Journal of Solid-State Circuits
Volume55
Issue number9
DOIs
Publication statusPublished - 2020 Sep

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'A 0.07-mm<sup>2</sup>162-mW DAC Achieving >65 dBc SFDR and < -70 dBc IM3 at 10 GS/s with Output Impedance Compensation and Concentric Parallelogram Routing'. Together they form a unique fingerprint.

  • Cite this