A 0.07mm2 210mW Single-1.1V-Supply 14-bit 10GS/s DAC with Concentric Parallelogram Routing and Output Impedance Compensation

Hung-yi Huang, Tai-haur Kuo

Research output: Contribution to conferencePaper

Original languageEnglish
PagesC136-C137
DOIs
Publication statusPublished - 2019 Jun
Event2019 Symposium on VLSI Circuits - Kyoto, Japan
Duration: 2019 Jun 92019 Jun 14

Conference

Conference2019 Symposium on VLSI Circuits
Period19-06-0919-06-14

Cite this

@conference{1b987caa7fbc48c199bb7e808ebc1025,
title = "A 0.07mm2 210mW Single-1.1V-Supply 14-bit 10GS/s DAC with Concentric Parallelogram Routing and Output Impedance Compensation",
author = "Hung-yi Huang and Tai-haur Kuo",
year = "2019",
month = "6",
doi = "10.23919/VLSIC.2019.8778067",
language = "English",
pages = "C136--C137",
note = "2019 Symposium on VLSI Circuits ; Conference date: 09-06-2019 Through 14-06-2019",

}

A 0.07mm2 210mW Single-1.1V-Supply 14-bit 10GS/s DAC with Concentric Parallelogram Routing and Output Impedance Compensation. / Huang, Hung-yi; Kuo, Tai-haur.

2019. C136-C137 Paper presented at 2019 Symposium on VLSI Circuits, .

Research output: Contribution to conferencePaper

TY - CONF

T1 - A 0.07mm2 210mW Single-1.1V-Supply 14-bit 10GS/s DAC with Concentric Parallelogram Routing and Output Impedance Compensation

AU - Huang, Hung-yi

AU - Kuo, Tai-haur

PY - 2019/6

Y1 - 2019/6

U2 - 10.23919/VLSIC.2019.8778067

DO - 10.23919/VLSIC.2019.8778067

M3 - Paper

SP - C136-C137

ER -