TY - GEN
T1 - A 0.07mm2 210mW Single-1.1V-Supply 14-bit 10GS/s DAC with Concentric Parallelogram Routing and Output Impedance Compensation
AU - Huang, Hung Yi
AU - Kuo, Tai Haur
N1 - Funding Information:
The authors would like to acknowledge chip fabrication support provided by Taiwan Semiconductor Research Institute (TSRI), Taiwan.
Publisher Copyright:
© 2019 JSAP.
PY - 2019/6
Y1 - 2019/6
N2 - A DAC with small-size non-cascoded current cells is proposed to achieve small area, low power, high linearity, and wide bandwidth. The proposed concentric parallelogram routing (CPR) reduces mismatch and timing skew among cells. In addition, the proposed output impedance compensation (OIC) remedies the insufficient output impedance of the noncascoded current cells. The DAC, implemented in 28nm CMOS process, achieves \gt64 dB SFDR over the entire Nyquist bandwidth at 10GS/s while consuming 210mW from a single 1.1V supply. Compared with other state-of-the-art CMOS DACs with resolutions higher than 10bit and Nyquist bandwidths over 3.4GHz, this DAC has an active area of only 0.07mm2 less than 1/12 of the others and the best performance for a commonly-used figure-of-merit (FoM).
AB - A DAC with small-size non-cascoded current cells is proposed to achieve small area, low power, high linearity, and wide bandwidth. The proposed concentric parallelogram routing (CPR) reduces mismatch and timing skew among cells. In addition, the proposed output impedance compensation (OIC) remedies the insufficient output impedance of the noncascoded current cells. The DAC, implemented in 28nm CMOS process, achieves \gt64 dB SFDR over the entire Nyquist bandwidth at 10GS/s while consuming 210mW from a single 1.1V supply. Compared with other state-of-the-art CMOS DACs with resolutions higher than 10bit and Nyquist bandwidths over 3.4GHz, this DAC has an active area of only 0.07mm2 less than 1/12 of the others and the best performance for a commonly-used figure-of-merit (FoM).
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U2 - 10.23919/VLSIC.2019.8778067
DO - 10.23919/VLSIC.2019.8778067
M3 - Conference contribution
AN - SCOPUS:85073900163
T3 - IEEE Symposium on VLSI Circuits, Digest of Technical Papers
SP - C136-C137
BT - 2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 33rd Symposium on VLSI Circuits, VLSI Circuits 2019
Y2 - 9 June 2019 through 14 June 2019
ER -