A 0.07mm2 210mW Single-1.1V-Supply 14-bit 10GS/s DAC with Concentric Parallelogram Routing and Output Impedance Compensation

Hung Yi Huang, Tai Haur Kuo

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

A DAC with small-size non-cascoded current cells is proposed to achieve small area, low power, high linearity, and wide bandwidth. The proposed concentric parallelogram routing (CPR) reduces mismatch and timing skew among cells. In addition, the proposed output impedance compensation (OIC) remedies the insufficient output impedance of the noncascoded current cells. The DAC, implemented in 28nm CMOS process, achieves \gt64 dB SFDR over the entire Nyquist bandwidth at 10GS/s while consuming 210mW from a single 1.1V supply. Compared with other state-of-the-art CMOS DACs with resolutions higher than 10bit and Nyquist bandwidths over 3.4GHz, this DAC has an active area of only 0.07mm2 less than 1/12 of the others and the best performance for a commonly-used figure-of-merit (FoM).

Original languageEnglish
Title of host publication2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers
PublisherInstitute of Electrical and Electronics Engineers Inc.
PagesC136-C137
ISBN (Electronic)9784863487185
DOIs
Publication statusPublished - 2019 Jun
Event33rd Symposium on VLSI Circuits, VLSI Circuits 2019 - Kyoto, Japan
Duration: 2019 Jun 92019 Jun 14

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers
Volume2019-June

Conference

Conference33rd Symposium on VLSI Circuits, VLSI Circuits 2019
CountryJapan
CityKyoto
Period19-06-0919-06-14

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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