A 0.35-1 V 0.2-3 GS/s 4-bit low-power flash ADC for a solar-powered wireless module

Ying Z. Lin, Yu Chang Lien, Soon-Jyh Chang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

This paper reports a 4-bit flash ADC with a supply range from 0.35 to 1 V. The corresponding sampling rates are 0.2 to 3 GS/s. This low-voltage low-power ADC is a feasible building block for a solar-powered wireless module. Passive subtraction by resistor ladders replaces active subtraction by 4-input preamplifiers since the linearity of ladders is independent of supply voltage. Passive subtraction and low-threshold devices enable low-supply operation. At 1.2 GS/s, the ADC consumes 1.93 mW from a 0.6-V supply. The ENOB is 3.60 bit and ERBW is 550 MHz, resulting in an FOM of 145 fJ/conversion-step.

Original languageEnglish
Title of host publicationProceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010
Pages299-302
Number of pages4
DOIs
Publication statusPublished - 2010 Nov 8
Event2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010 - Hsin Chu, Taiwan
Duration: 2010 Apr 262010 Apr 29

Publication series

NameProceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010

Other

Other2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010
CountryTaiwan
CityHsin Chu
Period10-04-2610-04-29

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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