A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS

Tay Jyi Lin, Cheng An Chien, Pei Yao Chang, Ching Wen Chen, Po Hao Wang, Ting Yu Shyu, Chien Yung Chou, Shien Chun Luo, Jiun In Guo, Tien Fu Chen, Gene C.H. Chuang, Yuan Hua Chu, Liang Chia Cheng, Hong Men Su, Chewnpu Jou, Meikei Ieong, Cheng Wen Wu, Jinn Shyan Wang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

19 Citations (Scopus)

Abstract

This paper presents a video recording SoC fabricated in 65nm low-power technology, which integrates a complexity and bandwidth-effective H.264 encoder, an ultra-low-power (ULP) MPU, with timing-optimized ROM and 8T SRAM macros for ultra-low-voltage (ULV) operation, a 512Kb ULV and leakage-aware 8T SRAM for the frame buffer (FB), and various on-chip peripherals, such as external memory interfaces (Fig. 9.3.1). Utilizing ULV cell libraries with custom-pulsed D flip-flops (PFF) for wide-range voltage scaling, ROM/SRAM macros optimized simultaneously for timing and leakage, and advanced energy management (AEM), the SoC achieves 32fps HD720 H.264 encoding at 1.0V, down to 0.57nJ/pixel ultra-low energy dissipation at 0.48V (30fps QQVGA H.264 encoding for preview through ANT+).

Original languageEnglish
Title of host publication2013 IEEE International Solid-State Circuits Conference, ISSCC 2013 - Digest of Technical Papers
Pages158-159
Number of pages2
DOIs
Publication statusPublished - 2013 Apr 29
Event2013 60th IEEE International Solid-State Circuits Conference, ISSCC 2013 - San Francisco, CA, United States
Duration: 2013 Feb 172013 Feb 21

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume56
ISSN (Print)0193-6530

Other

Other2013 60th IEEE International Solid-State Circuits Conference, ISSCC 2013
CountryUnited States
CitySan Francisco, CA
Period13-02-1713-02-21

Fingerprint

Video recording
Static random access storage
ROM
Pixels
Macros
Electric potential
Computer peripheral equipment
Flip flop circuits
Energy management
Interfaces (computer)
Energy dissipation
Buffers
Bandwidth
Data storage equipment
System-on-chip

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Lin, T. J., Chien, C. A., Chang, P. Y., Chen, C. W., Wang, P. H., Shyu, T. Y., ... Wang, J. S. (2013). A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS. In 2013 IEEE International Solid-State Circuits Conference, ISSCC 2013 - Digest of Technical Papers (pp. 158-159). [6487680] (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 56). https://doi.org/10.1109/ISSCC.2013.6487680
Lin, Tay Jyi ; Chien, Cheng An ; Chang, Pei Yao ; Chen, Ching Wen ; Wang, Po Hao ; Shyu, Ting Yu ; Chou, Chien Yung ; Luo, Shien Chun ; Guo, Jiun In ; Chen, Tien Fu ; Chuang, Gene C.H. ; Chu, Yuan Hua ; Cheng, Liang Chia ; Su, Hong Men ; Jou, Chewnpu ; Ieong, Meikei ; Wu, Cheng Wen ; Wang, Jinn Shyan. / A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS. 2013 IEEE International Solid-State Circuits Conference, ISSCC 2013 - Digest of Technical Papers. 2013. pp. 158-159 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).
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title = "A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS",
abstract = "This paper presents a video recording SoC fabricated in 65nm low-power technology, which integrates a complexity and bandwidth-effective H.264 encoder, an ultra-low-power (ULP) MPU, with timing-optimized ROM and 8T SRAM macros for ultra-low-voltage (ULV) operation, a 512Kb ULV and leakage-aware 8T SRAM for the frame buffer (FB), and various on-chip peripherals, such as external memory interfaces (Fig. 9.3.1). Utilizing ULV cell libraries with custom-pulsed D flip-flops (PFF) for wide-range voltage scaling, ROM/SRAM macros optimized simultaneously for timing and leakage, and advanced energy management (AEM), the SoC achieves 32fps HD720 H.264 encoding at 1.0V, down to 0.57nJ/pixel ultra-low energy dissipation at 0.48V (30fps QQVGA H.264 encoding for preview through ANT+).",
author = "Lin, {Tay Jyi} and Chien, {Cheng An} and Chang, {Pei Yao} and Chen, {Ching Wen} and Wang, {Po Hao} and Shyu, {Ting Yu} and Chou, {Chien Yung} and Luo, {Shien Chun} and Guo, {Jiun In} and Chen, {Tien Fu} and Chuang, {Gene C.H.} and Chu, {Yuan Hua} and Cheng, {Liang Chia} and Su, {Hong Men} and Chewnpu Jou and Meikei Ieong and Wu, {Cheng Wen} and Wang, {Jinn Shyan}",
year = "2013",
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doi = "10.1109/ISSCC.2013.6487680",
language = "English",
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Lin, TJ, Chien, CA, Chang, PY, Chen, CW, Wang, PH, Shyu, TY, Chou, CY, Luo, SC, Guo, JI, Chen, TF, Chuang, GCH, Chu, YH, Cheng, LC, Su, HM, Jou, C, Ieong, M, Wu, CW & Wang, JS 2013, A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS. in 2013 IEEE International Solid-State Circuits Conference, ISSCC 2013 - Digest of Technical Papers., 6487680, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, vol. 56, pp. 158-159, 2013 60th IEEE International Solid-State Circuits Conference, ISSCC 2013, San Francisco, CA, United States, 13-02-17. https://doi.org/10.1109/ISSCC.2013.6487680

A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS. / Lin, Tay Jyi; Chien, Cheng An; Chang, Pei Yao; Chen, Ching Wen; Wang, Po Hao; Shyu, Ting Yu; Chou, Chien Yung; Luo, Shien Chun; Guo, Jiun In; Chen, Tien Fu; Chuang, Gene C.H.; Chu, Yuan Hua; Cheng, Liang Chia; Su, Hong Men; Jou, Chewnpu; Ieong, Meikei; Wu, Cheng Wen; Wang, Jinn Shyan.

2013 IEEE International Solid-State Circuits Conference, ISSCC 2013 - Digest of Technical Papers. 2013. p. 158-159 6487680 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 56).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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T1 - A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS

AU - Lin, Tay Jyi

AU - Chien, Cheng An

AU - Chang, Pei Yao

AU - Chen, Ching Wen

AU - Wang, Po Hao

AU - Shyu, Ting Yu

AU - Chou, Chien Yung

AU - Luo, Shien Chun

AU - Guo, Jiun In

AU - Chen, Tien Fu

AU - Chuang, Gene C.H.

AU - Chu, Yuan Hua

AU - Cheng, Liang Chia

AU - Su, Hong Men

AU - Jou, Chewnpu

AU - Ieong, Meikei

AU - Wu, Cheng Wen

AU - Wang, Jinn Shyan

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N2 - This paper presents a video recording SoC fabricated in 65nm low-power technology, which integrates a complexity and bandwidth-effective H.264 encoder, an ultra-low-power (ULP) MPU, with timing-optimized ROM and 8T SRAM macros for ultra-low-voltage (ULV) operation, a 512Kb ULV and leakage-aware 8T SRAM for the frame buffer (FB), and various on-chip peripherals, such as external memory interfaces (Fig. 9.3.1). Utilizing ULV cell libraries with custom-pulsed D flip-flops (PFF) for wide-range voltage scaling, ROM/SRAM macros optimized simultaneously for timing and leakage, and advanced energy management (AEM), the SoC achieves 32fps HD720 H.264 encoding at 1.0V, down to 0.57nJ/pixel ultra-low energy dissipation at 0.48V (30fps QQVGA H.264 encoding for preview through ANT+).

AB - This paper presents a video recording SoC fabricated in 65nm low-power technology, which integrates a complexity and bandwidth-effective H.264 encoder, an ultra-low-power (ULP) MPU, with timing-optimized ROM and 8T SRAM macros for ultra-low-voltage (ULV) operation, a 512Kb ULV and leakage-aware 8T SRAM for the frame buffer (FB), and various on-chip peripherals, such as external memory interfaces (Fig. 9.3.1). Utilizing ULV cell libraries with custom-pulsed D flip-flops (PFF) for wide-range voltage scaling, ROM/SRAM macros optimized simultaneously for timing and leakage, and advanced energy management (AEM), the SoC achieves 32fps HD720 H.264 encoding at 1.0V, down to 0.57nJ/pixel ultra-low energy dissipation at 0.48V (30fps QQVGA H.264 encoding for preview through ANT+).

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DO - 10.1109/ISSCC.2013.6487680

M3 - Conference contribution

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BT - 2013 IEEE International Solid-State Circuits Conference, ISSCC 2013 - Digest of Technical Papers

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Lin TJ, Chien CA, Chang PY, Chen CW, Wang PH, Shyu TY et al. A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS. In 2013 IEEE International Solid-State Circuits Conference, ISSCC 2013 - Digest of Technical Papers. 2013. p. 158-159. 6487680. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). https://doi.org/10.1109/ISSCC.2013.6487680