Abstract
For implantable biosensor applications which require a low-cost signal processing unit that features ultra-low power and low-voltage capability as well, this paper proposes a solution by merging switched-opamp technique and foreground digital calibration into a single 10-bit ADC. Utilization of the switched-opamp technique allows for low supply operation down to 0.7 V. The insufficient gain associated with low supply voltage analog devices is manipulated by the employment of foreground calibration. Ultra-low power consumption is achieved through adequate circuit structure selection and weak-inversion transistor biasing. The ADC employs the cyclic/algorithmic architecture which uses only two opamps and two comparators. Simulation results with CMOS 0.13 μm process model demonstrate that the signal to noise and distortion ratio (SNDR) at 10-KHz clock rate is 57 dB when 0.5 % capacitor mismatch is considered. The power consumption of the whole ADC is 3 μW with 0.7 V supply.
| Original language | English |
|---|---|
| Title of host publication | IEEE 2006 Biomedical Circuits and Systems Conference Healthcare Technology, BioCAS 2006 |
| Pages | 122-125 |
| Number of pages | 4 |
| DOIs | |
| Publication status | Published - 2006 Dec 1 |
| Event | IEEE 2006 Biomedical Circuits and Systems Conference Healthcare Technology, BioCAS 2006 - London, United Kingdom Duration: 2006 Nov 29 → 2006 Dec 1 |
Publication series
| Name | IEEE 2006 Biomedical Circuits and Systems Conference Healthcare Technology, BioCAS 2006 |
|---|
Other
| Other | IEEE 2006 Biomedical Circuits and Systems Conference Healthcare Technology, BioCAS 2006 |
|---|---|
| Country | United Kingdom |
| City | London |
| Period | 06-11-29 → 06-12-01 |
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All Science Journal Classification (ASJC) codes
- Biomedical Engineering
- Electrical and Electronic Engineering
Cite this
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A 0.7-V 10-bit 3μW analog-to-digital converter for implantable biomedical applications. / Ou, Hsin Hung; Chen, Ya Chi; Liu, Bin Da.
IEEE 2006 Biomedical Circuits and Systems Conference Healthcare Technology, BioCAS 2006. 2006. p. 122-125 4600323 (IEEE 2006 Biomedical Circuits and Systems Conference Healthcare Technology, BioCAS 2006).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - A 0.7-V 10-bit 3μW analog-to-digital converter for implantable biomedical applications
AU - Ou, Hsin Hung
AU - Chen, Ya Chi
AU - Liu, Bin Da
PY - 2006/12/1
Y1 - 2006/12/1
N2 - For implantable biosensor applications which require a low-cost signal processing unit that features ultra-low power and low-voltage capability as well, this paper proposes a solution by merging switched-opamp technique and foreground digital calibration into a single 10-bit ADC. Utilization of the switched-opamp technique allows for low supply operation down to 0.7 V. The insufficient gain associated with low supply voltage analog devices is manipulated by the employment of foreground calibration. Ultra-low power consumption is achieved through adequate circuit structure selection and weak-inversion transistor biasing. The ADC employs the cyclic/algorithmic architecture which uses only two opamps and two comparators. Simulation results with CMOS 0.13 μm process model demonstrate that the signal to noise and distortion ratio (SNDR) at 10-KHz clock rate is 57 dB when 0.5 % capacitor mismatch is considered. The power consumption of the whole ADC is 3 μW with 0.7 V supply.
AB - For implantable biosensor applications which require a low-cost signal processing unit that features ultra-low power and low-voltage capability as well, this paper proposes a solution by merging switched-opamp technique and foreground digital calibration into a single 10-bit ADC. Utilization of the switched-opamp technique allows for low supply operation down to 0.7 V. The insufficient gain associated with low supply voltage analog devices is manipulated by the employment of foreground calibration. Ultra-low power consumption is achieved through adequate circuit structure selection and weak-inversion transistor biasing. The ADC employs the cyclic/algorithmic architecture which uses only two opamps and two comparators. Simulation results with CMOS 0.13 μm process model demonstrate that the signal to noise and distortion ratio (SNDR) at 10-KHz clock rate is 57 dB when 0.5 % capacitor mismatch is considered. The power consumption of the whole ADC is 3 μW with 0.7 V supply.
UR - http://www.scopus.com/inward/record.url?scp=52949153291&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=52949153291&partnerID=8YFLogxK
U2 - 10.1109/BIOCAS.2006.4600323
DO - 10.1109/BIOCAS.2006.4600323
M3 - Conference contribution
AN - SCOPUS:52949153291
SN - 1424404371
SN - 9781424404377
T3 - IEEE 2006 Biomedical Circuits and Systems Conference Healthcare Technology, BioCAS 2006
SP - 122
EP - 125
BT - IEEE 2006 Biomedical Circuits and Systems Conference Healthcare Technology, BioCAS 2006
ER -