Abstract
This paper proposes a low-voltage high-speed sample-and-hold (S/H) structure with excellent power efficiency. Based on the switched-opamp technique, an inverse-flip-around architecture which maximizes the feedback factor is employed in the proposed S/H. A skew-insensitive double-sampling mechanism is presented to increase the throughput by a factor of two while eliminating the timing mismatch associated with double-sampling circuits. Furthermore, a dual-input dual-output opamp is proposed to incorporate double-sampling into the switched-opamp based S/H. This opamp also removes the memory effect in double-sampling circuitry and features fast turn-on time to improve the speed performance in switched-opamp circuits. Simulation results using a 0.13-μm CMOS process model demonstrates the proposed S/H circuit has a total-harmonic-distortion of -67.3dB up to 250MSample/s and a 0.8V PP input range at 0.8V supply. The power consumption is 3.5mW and the figure-of-merit is only 7.4fJ/step.
Original language | English |
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Pages (from-to) | 1480-1487 |
Number of pages | 8 |
Journal | IEICE Transactions on Electronics |
Volume | E91-C |
Issue number | 9 |
DOIs | |
Publication status | Published - 2008 Sept |
All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering