A 0.9-V 11-bit 25-MS/s binary-search SAR ADC in 90-nm CMOS

Ying Zu Lin, Soon-Jyh Chang, Ya Ting Shyu, Guan Ying Huang, Chun Cheng Liu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

14 Citations (Scopus)

Abstract

This paper presents a new subrange analog-to-digital converter (ADC): a binary-search coarse ADC + a SAR fine ADC. The binary-search ADC improves conversion speed and gives coarse capacitors longer settling time. This ADC uses an RC hybrid DAC to reduce the unit capacitor count by 2. The rotation function of coarse capacitors enhances capacitor array linearity. The prototype in 90-nm CMOS only occupies an active area of 0.06 mm 2. From a 0.9-V supply, the power consumption is 0.32 and 0.58 mW at 10 and 25 MS/s, respectively. At 10 MS/s, the peak ENOB is 10.2 bit. At 25 MS/s, the peak ENOB is 9.9 bit and FOM is 29 fJ/conversion-step.

Original languageEnglish
Title of host publication2011 Proceedings of Technical Papers
Subtitle of host publicationIEEE Asian Solid-State Circuits Conference 2011, A-SSCC 2011
Pages69-72
Number of pages4
DOIs
Publication statusPublished - 2011 Dec 1
Event7th IEEE Asian Solid-State Circuits Conference, A-SSCC 2011 - Jeju, Korea, Republic of
Duration: 2011 Nov 142011 Nov 16

Publication series

Name2011 Proceedings of Technical Papers: IEEE Asian Solid-State Circuits Conference 2011, A-SSCC 2011

Other

Other7th IEEE Asian Solid-State Circuits Conference, A-SSCC 2011
CountryKorea, Republic of
CityJeju
Period11-11-1411-11-16

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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