TY - GEN

T1 - A 0.9-V 11-bit 25-MS/s binary-search SAR ADC in 90-nm CMOS

AU - Lin, Ying Zu

AU - Chang, Soon-Jyh

AU - Shyu, Ya Ting

AU - Huang, Guan Ying

AU - Liu, Chun Cheng

PY - 2011/12/1

Y1 - 2011/12/1

N2 - This paper presents a new subrange analog-to-digital converter (ADC): a binary-search coarse ADC + a SAR fine ADC. The binary-search ADC improves conversion speed and gives coarse capacitors longer settling time. This ADC uses an RC hybrid DAC to reduce the unit capacitor count by 2. The rotation function of coarse capacitors enhances capacitor array linearity. The prototype in 90-nm CMOS only occupies an active area of 0.06 mm 2. From a 0.9-V supply, the power consumption is 0.32 and 0.58 mW at 10 and 25 MS/s, respectively. At 10 MS/s, the peak ENOB is 10.2 bit. At 25 MS/s, the peak ENOB is 9.9 bit and FOM is 29 fJ/conversion-step.

AB - This paper presents a new subrange analog-to-digital converter (ADC): a binary-search coarse ADC + a SAR fine ADC. The binary-search ADC improves conversion speed and gives coarse capacitors longer settling time. This ADC uses an RC hybrid DAC to reduce the unit capacitor count by 2. The rotation function of coarse capacitors enhances capacitor array linearity. The prototype in 90-nm CMOS only occupies an active area of 0.06 mm 2. From a 0.9-V supply, the power consumption is 0.32 and 0.58 mW at 10 and 25 MS/s, respectively. At 10 MS/s, the peak ENOB is 10.2 bit. At 25 MS/s, the peak ENOB is 9.9 bit and FOM is 29 fJ/conversion-step.

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U2 - 10.1109/ASSCC.2011.6123606

DO - 10.1109/ASSCC.2011.6123606

M3 - Conference contribution

AN - SCOPUS:84863064232

SN - 9781467303989

T3 - 2011 Proceedings of Technical Papers: IEEE Asian Solid-State Circuits Conference 2011, A-SSCC 2011

SP - 69

EP - 72

BT - 2011 Proceedings of Technical Papers

T2 - 7th IEEE Asian Solid-State Circuits Conference, A-SSCC 2011

Y2 - 14 November 2011 through 16 November 2011

ER -