Abstract
This paper reports a 10-bit 50MS/s SAR ADC with a set-and-down capacitor switching method. Compared to the conventional method, the average switching energy is reduced about 81%. At 50MS/s and 1.2V supply, the ADC consumes 0.92mW and achieves an SNDR of 52.78dB, resulting in an FOM of 52fJ/Conversion-step. Fabricated in a 0.13uμm 1P8M CMOS technology, the ADC only occupies 0.075mm2 active area.
| Original language | English |
|---|---|
| Title of host publication | 2009 Symposium on VLSI Circuits |
| Pages | 236-237 |
| Number of pages | 2 |
| Publication status | Published - 2009 |
| Event | 2009 Symposium on VLSI Circuits - Kyoto, Japan Duration: 2009 Jun 16 → 2009 Jun 18 |
Other
| Other | 2009 Symposium on VLSI Circuits |
|---|---|
| Country | Japan |
| City | Kyoto |
| Period | 09-06-16 → 09-06-18 |
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All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering
Cite this
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A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13uμm CMOS process. / Liu, Chun Cheng; Chang, Soon-Jyh; Huang, Guan Ying; Lin, Yin Zu.
2009 Symposium on VLSI Circuits. 2009. p. 236-237 5205343.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13uμm CMOS process
AU - Liu, Chun Cheng
AU - Chang, Soon-Jyh
AU - Huang, Guan Ying
AU - Lin, Yin Zu
PY - 2009
Y1 - 2009
N2 - This paper reports a 10-bit 50MS/s SAR ADC with a set-and-down capacitor switching method. Compared to the conventional method, the average switching energy is reduced about 81%. At 50MS/s and 1.2V supply, the ADC consumes 0.92mW and achieves an SNDR of 52.78dB, resulting in an FOM of 52fJ/Conversion-step. Fabricated in a 0.13uμm 1P8M CMOS technology, the ADC only occupies 0.075mm2 active area.
AB - This paper reports a 10-bit 50MS/s SAR ADC with a set-and-down capacitor switching method. Compared to the conventional method, the average switching energy is reduced about 81%. At 50MS/s and 1.2V supply, the ADC consumes 0.92mW and achieves an SNDR of 52.78dB, resulting in an FOM of 52fJ/Conversion-step. Fabricated in a 0.13uμm 1P8M CMOS technology, the ADC only occupies 0.075mm2 active area.
UR - http://www.scopus.com/inward/record.url?scp=70449359767&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=70449359767&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:70449359767
SN - 9784863480018
SP - 236
EP - 237
BT - 2009 Symposium on VLSI Circuits
ER -