A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13uμm CMOS process

Chun Cheng Liu, Soon-Jyh Chang, Guan Ying Huang, Yin Zu Lin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

103 Citations (Scopus)

Abstract

This paper reports a 10-bit 50MS/s SAR ADC with a set-and-down capacitor switching method. Compared to the conventional method, the average switching energy is reduced about 81%. At 50MS/s and 1.2V supply, the ADC consumes 0.92mW and achieves an SNDR of 52.78dB, resulting in an FOM of 52fJ/Conversion-step. Fabricated in a 0.13uμm 1P8M CMOS technology, the ADC only occupies 0.075mm2 active area.

Original languageEnglish
Title of host publication2009 Symposium on VLSI Circuits
Pages236-237
Number of pages2
Publication statusPublished - 2009
Event2009 Symposium on VLSI Circuits - Kyoto, Japan
Duration: 2009 Jun 162009 Jun 18

Other

Other2009 Symposium on VLSI Circuits
CountryJapan
CityKyoto
Period09-06-1609-06-18

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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