Abstract
This paper reports a 10-bit 50MS/s SAR ADC with a set-and-down capacitor switching method. Compared to the conventional method, the average switching energy is reduced about 81%. At 50MS/s and 1.2V supply, the ADC consumes 0.92mW and achieves an SNDR of 52.78dB, resulting in an FOM of 52fJ/Conversion-step. Fabricated in a 0.13uμm 1P8M CMOS technology, the ADC only occupies 0.075mm2 active area.
Original language | English |
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Title of host publication | 2009 Symposium on VLSI Circuits |
Pages | 236-237 |
Number of pages | 2 |
Publication status | Published - 2009 |
Event | 2009 Symposium on VLSI Circuits - Kyoto, Japan Duration: 2009 Jun 16 → 2009 Jun 18 |
Other
Other | 2009 Symposium on VLSI Circuits |
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Country/Territory | Japan |
City | Kyoto |
Period | 09-06-16 → 09-06-18 |
All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering