A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13uμm CMOS process

Chun Cheng Liu, Soon-Jyh Chang, Guan Ying Huang, Yin Zu Lin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

100 Citations (Scopus)

Abstract

This paper reports a 10-bit 50MS/s SAR ADC with a set-and-down capacitor switching method. Compared to the conventional method, the average switching energy is reduced about 81%. At 50MS/s and 1.2V supply, the ADC consumes 0.92mW and achieves an SNDR of 52.78dB, resulting in an FOM of 52fJ/Conversion-step. Fabricated in a 0.13uμm 1P8M CMOS technology, the ADC only occupies 0.075mm2 active area.

Original languageEnglish
Title of host publication2009 Symposium on VLSI Circuits
Pages236-237
Number of pages2
Publication statusPublished - 2009
Event2009 Symposium on VLSI Circuits - Kyoto, Japan
Duration: 2009 Jun 162009 Jun 18

Other

Other2009 Symposium on VLSI Circuits
CountryJapan
CityKyoto
Period09-06-1609-06-18

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Capacitors

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Liu, C. C., Chang, S-J., Huang, G. Y., & Lin, Y. Z. (2009). A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13uμm CMOS process. In 2009 Symposium on VLSI Circuits (pp. 236-237). [5205343]
Liu, Chun Cheng ; Chang, Soon-Jyh ; Huang, Guan Ying ; Lin, Yin Zu. / A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13uμm CMOS process. 2009 Symposium on VLSI Circuits. 2009. pp. 236-237
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abstract = "This paper reports a 10-bit 50MS/s SAR ADC with a set-and-down capacitor switching method. Compared to the conventional method, the average switching energy is reduced about 81{\%}. At 50MS/s and 1.2V supply, the ADC consumes 0.92mW and achieves an SNDR of 52.78dB, resulting in an FOM of 52fJ/Conversion-step. Fabricated in a 0.13uμm 1P8M CMOS technology, the ADC only occupies 0.075mm2 active area.",
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Liu, CC, Chang, S-J, Huang, GY & Lin, YZ 2009, A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13uμm CMOS process. in 2009 Symposium on VLSI Circuits., 5205343, pp. 236-237, 2009 Symposium on VLSI Circuits, Kyoto, Japan, 09-06-16.

A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13uμm CMOS process. / Liu, Chun Cheng; Chang, Soon-Jyh; Huang, Guan Ying; Lin, Yin Zu.

2009 Symposium on VLSI Circuits. 2009. p. 236-237 5205343.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Liu CC, Chang S-J, Huang GY, Lin YZ. A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13uμm CMOS process. In 2009 Symposium on VLSI Circuits. 2009. p. 236-237. 5205343