TY - GEN
T1 - A 0.98-nW/kHz 33-kHz Fully Integrated Subthreshold-Region Operation RC Oscillator with Forward-Body-Biasing
AU - Fan, Philex Ming Yan
AU - Savanth, Anand
AU - Labbe, Benoit
AU - Prabhat, Pranay
AU - Myers, James
N1 - Funding Information:
Manuscript received May 30, 2019; revised July 22, 2019; accepted August 6, 2019. Date of publication October 15, 2019; date of current version October 15, 2019. This article was approved by Associate Editor Jens Anders. This work was supported by the Defense Advanced Research Projects Agency. (Corresponding author: Philex Ming-Yan Fan.) The authors are with Arm Research, Arm Ltd., Cambridge CB1 9NJ, U.K. (e-mail: philex.fan@arm.com). Digital Object Identifier 10.1109/LSSC.2019.2935571 Fig. 1. RCO, including (a) an adapted version from [4] and (b) proposed subthreshold-region operation with FBB.
Publisher Copyright:
© 2019 IEEE.
PY - 2019/9
Y1 - 2019/9
N2 - The lower bound on the power expended by an RC relaxation oscillator is decided by the RC network. This can be minimized by reducing the oscillation swing and increasing R. In the former technique,tighter comparator constraints limit power benefits while the latter technique increases resistor thermal noise bounding long-term jitter. To this end,this letter presents a fully integrated RC oscillator with core voltage aggressively scaled to subthreshold levels. A self-clocked switched-capacitor network is used to minimize voltage drop-out power loss. Full forward-body-biasing technique helps reduce device on-resistance. Additionally,temperature coefficient compensation for time constant is accomplished by poly resistors and a VTH-tracking reference scheme which avoids the use of diffusion resistors. This design is silicon-proven on 65-nm CMOS (0.0356-mm2 area). The implementation has a 33-kHz clock with 32.2 nW at 1.2 V. Line sensitivity is within +0.7/-0.6% per volt across 16 samples for 1 to 1.5 V. Temperature sensitivity was measured to be 56 ppm/°C from 0 °C to 85 °C and measured Allan deviation <100 ppm for averaging interval of τ = 400 s and <40 ppm for τ = 3000 s.
AB - The lower bound on the power expended by an RC relaxation oscillator is decided by the RC network. This can be minimized by reducing the oscillation swing and increasing R. In the former technique,tighter comparator constraints limit power benefits while the latter technique increases resistor thermal noise bounding long-term jitter. To this end,this letter presents a fully integrated RC oscillator with core voltage aggressively scaled to subthreshold levels. A self-clocked switched-capacitor network is used to minimize voltage drop-out power loss. Full forward-body-biasing technique helps reduce device on-resistance. Additionally,temperature coefficient compensation for time constant is accomplished by poly resistors and a VTH-tracking reference scheme which avoids the use of diffusion resistors. This design is silicon-proven on 65-nm CMOS (0.0356-mm2 area). The implementation has a 33-kHz clock with 32.2 nW at 1.2 V. Line sensitivity is within +0.7/-0.6% per volt across 16 samples for 1 to 1.5 V. Temperature sensitivity was measured to be 56 ppm/°C from 0 °C to 85 °C and measured Allan deviation <100 ppm for averaging interval of τ = 400 s and <40 ppm for τ = 3000 s.
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U2 - 10.1109/ESSCIRC.2019.8902906
DO - 10.1109/ESSCIRC.2019.8902906
M3 - Conference contribution
AN - SCOPUS:85075941696
T3 - ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference
SP - 175
EP - 178
BT - ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 45th IEEE European Solid State Circuits Conference, ESSCIRC 2019
Y2 - 23 September 2019 through 26 September 2019
ER -