TY - JOUR
T1 - A 1-μW 10-bit 200-kS/s SAR ADC with a bypass window for biomedical applications
AU - Huang, Guan Ying
AU - Chang, Soon Jyh
AU - Liu, Chun Cheng
AU - Lin, Ying Zu
N1 - Funding Information:
Manuscript received December 22, 2011; revised May 27, 2012; accepted July 29, 2012. Date of current version October 26, 2012. This work was supported in part by the National Science Council of Taiwan under Grant NSC 98-2221-E-006-156-MY3 and by Himax Technologies Inc., Taiwan. This paper was approved by Associate Editor Roland Thewes.
PY - 2012
Y1 - 2012
N2 - This paper presents an energy efficient successive-approximation-register (SAR) analog-to-digital converter (ADC) for biomedical applications. To reduce energy consumption, a bypass window technique is used to select switching sequences to skip several conversion steps when the signal is within a predefined small window. The power consumptions of the capacitive digital-to-analog converter (DAC), latch comparator, and digital control circuit of the proposed ADC are lower than those of a conventional SAR ADC. The proposed bypass window tolerates the DAC settling error and comparator voltage offset in the first four phases and suppresses the peak DNL and INL values. A proof-of-concept prototype was fabricated in 0.18-μm 1P6M CMOS technology. At a 0.6-V supply voltage and a 200-kS/s sampling rate, the ADC achieves a signal-to-noise and distortion ratio of 57.97 dB and consumes 1.04 μW, resulting in a figure of merit of 8.03 fJ/conversion-step. The ADC core occupies an active area of only 0.082 mm2.
AB - This paper presents an energy efficient successive-approximation-register (SAR) analog-to-digital converter (ADC) for biomedical applications. To reduce energy consumption, a bypass window technique is used to select switching sequences to skip several conversion steps when the signal is within a predefined small window. The power consumptions of the capacitive digital-to-analog converter (DAC), latch comparator, and digital control circuit of the proposed ADC are lower than those of a conventional SAR ADC. The proposed bypass window tolerates the DAC settling error and comparator voltage offset in the first four phases and suppresses the peak DNL and INL values. A proof-of-concept prototype was fabricated in 0.18-μm 1P6M CMOS technology. At a 0.6-V supply voltage and a 200-kS/s sampling rate, the ADC achieves a signal-to-noise and distortion ratio of 57.97 dB and consumes 1.04 μW, resulting in a figure of merit of 8.03 fJ/conversion-step. The ADC core occupies an active area of only 0.082 mm2.
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U2 - 10.1109/JSSC.2012.2217635
DO - 10.1109/JSSC.2012.2217635
M3 - Article
AN - SCOPUS:84869155414
VL - 47
SP - 2783
EP - 2795
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
SN - 0018-9200
IS - 11
M1 - 6339066
ER -
