A 1-V 2.4-GHz low-power fractional-N frequency synthesizer with sigma-delta modulator controller

Shuenn Yuh Lee; Chung Han Cheng; Ming Feng Huang; Shyh Chyang Lee

doi:10.1109/ISCAS.2005.1465211

A 1-V 2.4-GHz low-power fractional-N frequency synthesizer with sigma-delta modulator controller

Shuenn Yuh Lee, Chung Han Cheng, Ming Feng Huang, Shyh Chyang Lee

Department of Electrical Engineering

Research output: Contribution to journal › Conference article › peer-review

7 Citations (Scopus)

Abstract

A 1-V low-power 2.4GHz fractional-N frequency synthesizer with sigma-delta modulator controller for Bluetooth applications is implemented in 0.18 μm CMOS technology. A novel structure dual-modulus divide-by-128/129 prescaler using dynamic D-flip-flop is proposed and the operating clock frequency can reach as high as 2.6 GHz at 1-V supply voltage. Moreover, a third-order feedforward sigmadelta modulator (SDM) is employed as a modulus controller to achieve an appropriate division ratio and suppress the fractional spurs. The simulation results show the synthesizer possesses the tuning range of 2.136 to 2.53 GHz and a phase noise of -126.85 dBc/Hz at 1MHz offset. Moreover, the core area without the SDM and the loop filter is 0.85 mm², and the total power consumption is 8.94 mW.

Original language	English
Article number	1465211
Pages (from-to)	2811-2814
Number of pages	4
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
DOIs	https://doi.org/10.1109/ISCAS.2005.1465211
Publication status	Published - 2005
Event	IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan Duration: 2005 May 23 → 2005 May 26

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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10.1109/ISCAS.2005.1465211

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title = "A 1-V 2.4-GHz low-power fractional-N frequency synthesizer with sigma-delta modulator controller",

abstract = "A 1-V low-power 2.4GHz fractional-N frequency synthesizer with sigma-delta modulator controller for Bluetooth applications is implemented in 0.18 μm CMOS technology. A novel structure dual-modulus divide-by-128/129 prescaler using dynamic D-flip-flop is proposed and the operating clock frequency can reach as high as 2.6 GHz at 1-V supply voltage. Moreover, a third-order feedforward sigmadelta modulator (SDM) is employed as a modulus controller to achieve an appropriate division ratio and suppress the fractional spurs. The simulation results show the synthesizer possesses the tuning range of 2.136 to 2.53 GHz and a phase noise of -126.85 dBc/Hz at 1MHz offset. Moreover, the core area without the SDM and the loop filter is 0.85 mm2, and the total power consumption is 8.94 mW.",

author = "Lee, {Shuenn Yuh} and Cheng, {Chung Han} and Huang, {Ming Feng} and Lee, {Shyh Chyang}",

year = "2005",

doi = "10.1109/ISCAS.2005.1465211",

language = "English",

pages = "2811--2814",

journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

issn = "0271-4310",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 ; Conference date: 23-05-2005 Through 26-05-2005",

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T1 - A 1-V 2.4-GHz low-power fractional-N frequency synthesizer with sigma-delta modulator controller

AU - Lee, Shuenn Yuh

AU - Cheng, Chung Han

AU - Huang, Ming Feng

AU - Lee, Shyh Chyang

PY - 2005

Y1 - 2005

N2 - A 1-V low-power 2.4GHz fractional-N frequency synthesizer with sigma-delta modulator controller for Bluetooth applications is implemented in 0.18 μm CMOS technology. A novel structure dual-modulus divide-by-128/129 prescaler using dynamic D-flip-flop is proposed and the operating clock frequency can reach as high as 2.6 GHz at 1-V supply voltage. Moreover, a third-order feedforward sigmadelta modulator (SDM) is employed as a modulus controller to achieve an appropriate division ratio and suppress the fractional spurs. The simulation results show the synthesizer possesses the tuning range of 2.136 to 2.53 GHz and a phase noise of -126.85 dBc/Hz at 1MHz offset. Moreover, the core area without the SDM and the loop filter is 0.85 mm2, and the total power consumption is 8.94 mW.

AB - A 1-V low-power 2.4GHz fractional-N frequency synthesizer with sigma-delta modulator controller for Bluetooth applications is implemented in 0.18 μm CMOS technology. A novel structure dual-modulus divide-by-128/129 prescaler using dynamic D-flip-flop is proposed and the operating clock frequency can reach as high as 2.6 GHz at 1-V supply voltage. Moreover, a third-order feedforward sigmadelta modulator (SDM) is employed as a modulus controller to achieve an appropriate division ratio and suppress the fractional spurs. The simulation results show the synthesizer possesses the tuning range of 2.136 to 2.53 GHz and a phase noise of -126.85 dBc/Hz at 1MHz offset. Moreover, the core area without the SDM and the loop filter is 0.85 mm2, and the total power consumption is 8.94 mW.

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JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

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T2 - IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005

Y2 - 23 May 2005 through 26 May 2005

ER -

A 1-V 2.4-GHz low-power fractional-N frequency synthesizer with sigma-delta modulator controller

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All Science Journal Classification (ASJC) codes

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