Abstract
This paper exploits the possibility to merge opamp-sharing technique into switched-opamp configuration. In a switched-opamp based design, the capacitors connected to the opamp output are not switchable, therefore the insertion of opamp-sharing technique demands two output stages within an opamp. A 1-V 9-bit 2.5-MSample/s pipelined analog-to-digital converter is designed to verify the proposed idea. Simulated with TSMC 0.35 μm CMOS 2P4M process models, the results show that differential nonlinearity and integral nonlinearity are 0.5 and 0.65 LSB, respectively. SNDR of pipelined ADC achieves 53.4 dB at 2.5 MHz clock rate. The power consumption is 15 mW at 1 V supply.
| Original language | English |
|---|---|
| Article number | 1465001 |
| Pages (from-to) | 1972-1975 |
| Number of pages | 4 |
| Journal | Proceedings - IEEE International Symposium on Circuits and Systems |
| DOIs | |
| Publication status | Published - 2005 Dec 1 |
| Event | IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan Duration: 2005 May 23 → 2005 May 26 |
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All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
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A 1-V, 9-bit, 2.5-M sample/s pipelined ADC with merged switched-opamp and opamp-sharing techniques. / Ou, Hsin Hung; Liu, Bin Da.
In: Proceedings - IEEE International Symposium on Circuits and Systems, 01.12.2005, p. 1972-1975.Research output: Contribution to journal › Conference article
TY - JOUR
T1 - A 1-V, 9-bit, 2.5-M sample/s pipelined ADC with merged switched-opamp and opamp-sharing techniques
AU - Ou, Hsin Hung
AU - Liu, Bin Da
PY - 2005/12/1
Y1 - 2005/12/1
N2 - This paper exploits the possibility to merge opamp-sharing technique into switched-opamp configuration. In a switched-opamp based design, the capacitors connected to the opamp output are not switchable, therefore the insertion of opamp-sharing technique demands two output stages within an opamp. A 1-V 9-bit 2.5-MSample/s pipelined analog-to-digital converter is designed to verify the proposed idea. Simulated with TSMC 0.35 μm CMOS 2P4M process models, the results show that differential nonlinearity and integral nonlinearity are 0.5 and 0.65 LSB, respectively. SNDR of pipelined ADC achieves 53.4 dB at 2.5 MHz clock rate. The power consumption is 15 mW at 1 V supply.
AB - This paper exploits the possibility to merge opamp-sharing technique into switched-opamp configuration. In a switched-opamp based design, the capacitors connected to the opamp output are not switchable, therefore the insertion of opamp-sharing technique demands two output stages within an opamp. A 1-V 9-bit 2.5-MSample/s pipelined analog-to-digital converter is designed to verify the proposed idea. Simulated with TSMC 0.35 μm CMOS 2P4M process models, the results show that differential nonlinearity and integral nonlinearity are 0.5 and 0.65 LSB, respectively. SNDR of pipelined ADC achieves 53.4 dB at 2.5 MHz clock rate. The power consumption is 15 mW at 1 V supply.
UR - http://www.scopus.com/inward/record.url?scp=67649122211&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=67649122211&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2005.1465001
DO - 10.1109/ISCAS.2005.1465001
M3 - Conference article
AN - SCOPUS:67649122211
SP - 1972
EP - 1975
JO - Proceedings - IEEE International Symposium on Circuits and Systems
JF - Proceedings - IEEE International Symposium on Circuits and Systems
SN - 0271-4310
M1 - 1465001
ER -