This paper exploits the possibility to merge opamp-sharing technique into switched-opamp configuration. In a switched-opamp based design, the capacitors connected to the opamp output are not switchable, therefore the insertion of opamp-sharing technique demands two output stages within an opamp. A 1-V 9-bit 2.5-MSample/s pipelined analog-to-digital converter is designed to verify the proposed idea. Simulated with TSMC 0.35 μm CMOS 2P4M process models, the results show that differential nonlinearity and integral nonlinearity are 0.5 and 0.65 LSB, respectively. SNDR of pipelined ADC achieves 53.4 dB at 2.5 MHz clock rate. The power consumption is 15 mW at 1 V supply.
|Number of pages||4|
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|Publication status||Published - 2005 Dec 1|
|Event||IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan|
Duration: 2005 May 23 → 2005 May 26
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering