A 1-V, 9-bit, 2.5-M sample/s pipelined ADC with merged switched-opamp and opamp-sharing techniques

Hsin Hung Ou; Bin Da Liu

doi:10.1109/ISCAS.2005.1465001

A 1-V, 9-bit, 2.5-M sample/s pipelined ADC with merged switched-opamp and opamp-sharing techniques

Hsin Hung Ou, Bin Da Liu

Department of Electrical Engineering

Research output: Contribution to journal › Conference article › peer-review

3 Citations (Scopus)

Abstract

This paper exploits the possibility to merge opamp-sharing technique into switched-opamp configuration. In a switched-opamp based design, the capacitors connected to the opamp output are not switchable, therefore the insertion of opamp-sharing technique demands two output stages within an opamp. A 1-V 9-bit 2.5-MSample/s pipelined analog-to-digital converter is designed to verify the proposed idea. Simulated with TSMC 0.35 μm CMOS 2P4M process models, the results show that differential nonlinearity and integral nonlinearity are 0.5 and 0.65 LSB, respectively. SNDR of pipelined ADC achieves 53.4 dB at 2.5 MHz clock rate. The power consumption is 15 mW at 1 V supply.

Original language	English
Article number	1465001
Pages (from-to)	1972-1975
Number of pages	4
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
DOIs	https://doi.org/10.1109/ISCAS.2005.1465001
Publication status	Published - 2005
Event	IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan Duration: 2005 May 23 → 2005 May 26

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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10.1109/ISCAS.2005.1465001

Cite this

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title = "A 1-V, 9-bit, 2.5-M sample/s pipelined ADC with merged switched-opamp and opamp-sharing techniques",

abstract = "This paper exploits the possibility to merge opamp-sharing technique into switched-opamp configuration. In a switched-opamp based design, the capacitors connected to the opamp output are not switchable, therefore the insertion of opamp-sharing technique demands two output stages within an opamp. A 1-V 9-bit 2.5-MSample/s pipelined analog-to-digital converter is designed to verify the proposed idea. Simulated with TSMC 0.35 μm CMOS 2P4M process models, the results show that differential nonlinearity and integral nonlinearity are 0.5 and 0.65 LSB, respectively. SNDR of pipelined ADC achieves 53.4 dB at 2.5 MHz clock rate. The power consumption is 15 mW at 1 V supply.",

author = "Ou, {Hsin Hung} and Liu, {Bin Da}",

year = "2005",

doi = "10.1109/ISCAS.2005.1465001",

language = "English",

pages = "1972--1975",

journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

issn = "0271-4310",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 ; Conference date: 23-05-2005 Through 26-05-2005",

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TY - JOUR

T1 - A 1-V, 9-bit, 2.5-M sample/s pipelined ADC with merged switched-opamp and opamp-sharing techniques

AU - Ou, Hsin Hung

AU - Liu, Bin Da

PY - 2005

Y1 - 2005

N2 - This paper exploits the possibility to merge opamp-sharing technique into switched-opamp configuration. In a switched-opamp based design, the capacitors connected to the opamp output are not switchable, therefore the insertion of opamp-sharing technique demands two output stages within an opamp. A 1-V 9-bit 2.5-MSample/s pipelined analog-to-digital converter is designed to verify the proposed idea. Simulated with TSMC 0.35 μm CMOS 2P4M process models, the results show that differential nonlinearity and integral nonlinearity are 0.5 and 0.65 LSB, respectively. SNDR of pipelined ADC achieves 53.4 dB at 2.5 MHz clock rate. The power consumption is 15 mW at 1 V supply.

AB - This paper exploits the possibility to merge opamp-sharing technique into switched-opamp configuration. In a switched-opamp based design, the capacitors connected to the opamp output are not switchable, therefore the insertion of opamp-sharing technique demands two output stages within an opamp. A 1-V 9-bit 2.5-MSample/s pipelined analog-to-digital converter is designed to verify the proposed idea. Simulated with TSMC 0.35 μm CMOS 2P4M process models, the results show that differential nonlinearity and integral nonlinearity are 0.5 and 0.65 LSB, respectively. SNDR of pipelined ADC achieves 53.4 dB at 2.5 MHz clock rate. The power consumption is 15 mW at 1 V supply.

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M3 - Conference article

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EP - 1975

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

M1 - 1465001

T2 - IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005

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ER -

A 1-V, 9-bit, 2.5-M sample/s pipelined ADC with merged switched-opamp and opamp-sharing techniques

Abstract

All Science Journal Classification (ASJC) codes

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