@inproceedings{a5d467d59b924419a389f365be8ca511,
title = "A 1 V CMOS analog comparator using auto-zero and complementary differential-input technique",
abstract = "A CMOS comparator operating over a 1 V to 5 V supply range is presented. No special low-voltage technology is used for fabrication. An experimental chip was fabricated using a 0.5 μm 5 V CMOS double-poly double-metal technology. The chip area of the comparator was 230×160 μm2. Measured results at 1 V supply voltage show a comparator response time of less than 4 μs for 10 mV precision. Static power consumptions at 1 V supply voltage including input/output pads for comparator is 1 μW.",
author = "Hung, {Yu Cherng} and Liu, {Bin Da}",
year = "2002",
month = jan,
day = "1",
doi = "10.1109/APASIC.2002.1031562",
language = "English",
series = "2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "181--184",
booktitle = "2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings",
address = "United States",
note = "3rd IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 ; Conference date: 06-08-2002 Through 08-08-2002",
}