A 1 V CMOS analog comparator using auto-zero and complementary differential-input technique

Yu Cherng Hung, Bin Da Liu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

A CMOS comparator operating over a 1 V to 5 V supply range is presented. No special low-voltage technology is used for fabrication. An experimental chip was fabricated using a 0.5 μm 5 V CMOS double-poly double-metal technology. The chip area of the comparator was 230×160 μm2. Measured results at 1 V supply voltage show a comparator response time of less than 4 μs for 10 mV precision. Static power consumptions at 1 V supply voltage including input/output pads for comparator is 1 μW.

Original languageEnglish
Title of host publication2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages181-184
Number of pages4
ISBN (Electronic)0780373634, 9780780373631
DOIs
Publication statusPublished - 2002 Jan 1
Event3rd IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Taipei, Taiwan
Duration: 2002 Aug 62002 Aug 8

Publication series

Name2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings

Other

Other3rd IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002
CountryTaiwan
CityTaipei
Period02-08-0602-08-08

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All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Hung, Y. C., & Liu, B. D. (2002). A 1 V CMOS analog comparator using auto-zero and complementary differential-input technique. In 2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings (pp. 181-184). [1031562] (2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APASIC.2002.1031562